Patents by Inventor Paul Baginski

Paul Baginski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Switching scheme for ISI mitigation in data converters
    Patent number: 9124283
    Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: September 1, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Abhishek Bandyopadhyay, Paul A. Baginski
  • SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS
    Publication number: 20150002322
    Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Applicant: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Paul A. Baginski
  • Switching scheme for ISI mitigation in data converters
    Patent number: 8847807
    Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Paul A. Baginski
  • SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS
    Publication number: 20140145867
    Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
    Type: Application
    Filed: March 8, 2013
    Publication date: May 29, 2014
    Applicant: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Paul A. Baginski
  • Architecture combining a continuous-time stage with a switched-capacitor stage for digital-to-analog converters and low-pass filters
    Patent number: 7423573
    Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: September 9, 2008
    Assignee: Analog Devices, Inc.
    Inventors: Paul A. Baginski, Robert Adams, Khiem Nguyen
  • ARCHITECTURE COMBINING A CONTINUOUS-TIME STAGE WITH A SWITCHED-CAPACITOR STAGE FOR DIGITAL-TO-ANALOG CONVERTERS AND LOW-PASS FILTERS
    Publication number: 20070159370
    Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 12, 2007
    Inventors: Paul Baginski, Robert Adams, Khiem Nguyen