Patents by Inventor Paul Bayer

Paul Bayer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4676868
    Abstract: A method for planarizing an insulating layer overlying an irregular topographic substrate, e.g., a conductive layer, is planarized by use of a sacrificial planarization layer. The planarization layer is removed using an oxygen-containing plasma generated in a parallel electrode reactor operating at a low excitation frequency and high pressure. Once the interface between the planarization layer and the conductive layer is reached, a second plasma with a reduced oxygen content is employed to avoid overetching the planarization layer. It has been observed that oxidizing species liberated during the etching of the insulating layer, typically silicon dioxide, contribute to the oxidation and hence removal of the planarization layer.
    Type: Grant
    Filed: April 23, 1986
    Date of Patent: June 30, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Paul E. Riley, Alan B. Ray, Paul Bayer