Abstract: The invention relates to a pressure compensation system having a safety function for an electrolytic tank of flow batteries, in particular, vanadium redox flow batteries, and a head portion (5) of the electrolytic tank (3, 4) is connected to the surrounding area (2) of the flow battery via a pipeline (6), in which a primary bi-directional pressure compensation valve (7) is situated, and a bypass line (9, 20), in which a secondary bi-directional pressure compensation valve (10) having a second response pressure greater than the first response pressure is situated, branches off from the pipeline (6) having the primary pressure compensation valve (7) having a first response pressure, and the outlet (11) of said bypass line is situated within a housing (13) surrounding the electrolytic tanks (3, 4).

Abstract: A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Abstract: Control of a communications path interconnecting separate devices in a digital computer system is provided by only two signals generated and received locally within each device on the path and asserted on a systems-wide basis on two separate lines of the path. The generation and utilization of the control signals is independent of the physical location of the devices on the path, and position-dependent delays in transmission of the signals from one device to another are avoided.

Abstract: A data processing system including a plurality of data units and a common bus. The data unit includes apparatus for issuing instructions including a LOCK instruction and an UNLOCK instruction. Each data unit includes apparatus responsive to the instructions such that, if the first data unit issues a LOCK instruction, the data unit other than the first data unit, are prevented from transferring information over the common bus with a LOCK instruction until an UNLOCK instruction is issued by any data unit.

Abstract: A data processing system in which a unit needing to be serviced by a processor first requests an interrupt and, after the interrupt is granted by the processor, requests access to a system bus to transfer interrupt information as it normally would transfer other information. The interrupting unit must wait for other units having higher priority to transfer information, usually memory information over the bus, before it can access the bus to transfer its interrupting information. This permits transfers of information having higher priority to occur before the transfer of the interrupt information is transferred.