Patents by Inventor Paul Bonwick

Paul Bonwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120081148
    Abstract: A programmable logic device includes a plurality of repeating units, each of which includes interconnecting lines, a logic block comprising logic circuits, and a configuration memory block including a plurality of configuration memory circuits. One of the plurality of repeating units includes: a selection device coupled to output data of the plurality of configuration memory circuits and a shift chain segment input; and a flip flop receiving output of the selection device to output a shift chain segment output.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventor: PAUL BONWICK
  • Patent number: 7852115
    Abstract: A method and apparatus for connecting a load track (3) of a programmable interconnect to a plurality of intersecting driver tracks (2) of the programmable interconnect. The apparatus comprises a chain of connection cells (9;15), each connection cell being operable to connect the load track of the programmable interconnect to an associated intersecting driver track. Each cell also comprises connection signal receiving means arranged to receive a connection signal and activation signal receiving means arranged to receive an activation signal. The apparatus also comprises connection means arranged to connect the load track of the programmable interconnect to the associated intersecting driver track of the programmable interconnect when the connection signal receiving means has received a connection signal and the activation signal receiving means has received an activation signal.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventor: Paul Bonwick
  • Publication number: 20100117681
    Abstract: A method and apparatus for connecting a load track (3) of a programmable interconnect to a plurality of intersecting driver tracks (2) of the programmable interconnect. The apparatus comprises a chain of connection cells (9;15), each connection cell being operable to connect the load track of the programmable interconnect to an associated intersecting driver track. Each cell also comprises connection signal receiving means arranged to receive a connection signal and activation signal receiving means arranged to receive an activation signal. The apparatus also comprises connection means arranged to connect the load track of the programmable interconnect to the associated intersecting driver track of the programmable interconnect when the connection signal receiving means has received a connection signal and the activation signal receiving means has received an activation signal.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 13, 2010
    Inventor: Paul BONWICK
  • Patent number: 7659786
    Abstract: A ring oscillator includes a first logic block having a first input connected to a specific point along a delay path, a first output and a second output, and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path, and a first output connected to the beginning of the delay path. The first logic block is arranged to alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to alternately select its first input and its second input every time a rising edge is input into its third input.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: February 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Paul Bonwick, Alan Marshall, Howard Sims, legal representative
  • Publication number: 20080309417
    Abstract: A ring oscillator comprises a first logic block having a first input connected to a specific point along a delay path, a first output and a second output and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path and a first output connected to the beginning of the delay path. The first logic block is arranged to, in use, alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to, in use, alternately select its first input and its second input every time a rising edge is input into its third input.
    Type: Application
    Filed: March 6, 2008
    Publication date: December 18, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Paul Bonwick, Alan Marshall, Howard Sims