Patents by Inventor Paul Brabant

Paul Brabant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140120678
    Abstract: The present invention addresses the key challenges in FinFET fabrication, that is, the fabrications of thin, uniform fins and also reducing the source/drain series resistance. More particularly, this application relates to FinFET fabrication techniques utilizing tetrasilane to enable conformal deposition with high doping using phosphate, arsenic and boron as dopants thereby creating thin fins having uniform thickness (uniformity across devices) as well as smooth, vertical sidewalls, while simultaneously reducing the parasitic series resistance.
    Type: Application
    Filed: October 25, 2013
    Publication date: May 1, 2014
    Applicant: MATHESON TRI-GAS
    Inventors: Manabu Shinriki, Paul Brabant, Keith Chung, JR.
  • Patent number: 8088225
    Abstract: A substrate support system comprises a substrate holder having a plurality of passages extending between top and bottom surfaces thereof. The substrate holder supports a peripheral portion of the substrate backside so that a thin gap is formed between the substrate and the substrate holder. A hollow support member provides support to an underside of, and is configured to convey gas upward into one or more of the passages of, the substrate holder. The upwardly conveyed gas flows into the gap between the substrate and the substrate holder. Depending upon the embodiment, the gas then flows either outward and upward around the substrate edge (to inhibit backside deposition of reactant gases above the substrate) or downward through passages of the substrate holder, if any, that do not lead back into the hollow support member (to inhibit autodoping by sweeping out-diffused dopant atoms away from the substrate backside).
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: January 3, 2012
    Assignee: ASM America, Inc.
    Inventors: Matt G. Goodman, Jereon Stoutyesdijk, Ravinder Aggarwal, Mike Halpin, Tony Keeton, Mark Hawkins, Lee Haen, Armand Ferro, Paul Brabant, Robert Vyne, Gregory M. Bartlett, Joseph P. Italiano, Bob Haro
  • Patent number: 7816236
    Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: October 19, 2010
    Assignee: ASM America Inc.
    Inventors: Matthias Bauer, Chantal Arena, Ronald Bertram, Pierre Tomasini, Nyles Cody, Paul Brabant, Joseph Italiano, Paul Jacobson, Keith Doran Weeks
  • Publication number: 20100089314
    Abstract: A substrate support system comprises a substrate holder having a plurality of passages extending between top and bottom surfaces thereof. The substrate holder supports a peripheral portion of the substrate backside so that a thin gap is formed between the substrate and the substrate holder. A hollow support member provides support to an underside of, and is configured to convey gas upward into one or more of the passages of, the substrate holder. The upwardly conveyed gas flows into the gap between the substrate and the substrate holder. Depending upon the embodiment, the gas then flows either outward and upward around the substrate edge (to inhibit backside deposition of reactant gases above the substrate) or downward through passages of the substrate holder, if any, that do not lead back into the hollow support member (to inhibit autodoping by sweeping out-diffused dopant atoms away from the substrate backside).
    Type: Application
    Filed: December 18, 2009
    Publication date: April 15, 2010
    Applicant: ASM AMERICA, INC.
    Inventors: Matt G. Goodman, Jereon Stoutyesdijk, Ravinder Aggarwal, Mike Halpin, Tony Keeton, Mark Hawkins, Lee Haen, Armand Ferro, Paul Brabant, Robert Vyne, Gregory M. Bartlett, Joseph P. Italiano, Bob Haro
  • Patent number: 7648579
    Abstract: A substrate support system comprises a substrate holder having a plurality of passages extending between top and bottom surfaces thereof. The substrate holder supports a peripheral portion of the substrate backside so that a thin gap is formed between the substrate and the substrate holder. A hollow support member provides support to an underside of, and is configured to convey gas upward into one or more of the passages of, the substrate holder. The upwardly conveyed gas flows into the gap between the substrate and the substrate holder. Depending upon the embodiment, the gas then flows either outward and upward around the substrate edge (to inhibit backside deposition of reactant gases above the substrate) or downward through passages of the substrate holder, if any, that do not lead back into the hollow support member (to inhibit autodoping by sweeping out-diffused dopant atoms away from the substrate backside).
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: January 19, 2010
    Assignee: ASM America, Inc.
    Inventors: Matt G. Goodman, Jereon Stoutyesdijk, Ravinder Aggarwal, Mike Halpin, Tony Keeton, Mark Hawkins, Lee Haen, Armand Ferro, Paul Brabant, Robert Vyne, Gregory M. Bartlett, Joseph P. Italiano, Bob Haro
  • Patent number: 7479443
    Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: January 20, 2009
    Assignee: ASM America Inc.
    Inventors: Matthias Bauer, Paul Brabant, Trevan Landin
  • Publication number: 20080081112
    Abstract: A reactor for processing a plurality of workpieces including a support for holding the plurality of workpieces, a first processing zone, one or more radiant heating elements adapted to heat a plurality of workpieces positioned in the first processing zone, a second processing zone, one or more resistive heating elements adapted to heat a plurality of workpieces positioned in the second processing zone, and an apparatus for moving the support between the first processing zone and the second processing zone.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Paul Brabant, Paul Jacobson
  • Patent number: 7329593
    Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 12, 2008
    Assignee: ASM America, Inc.
    Inventors: Matthias Bauer, Paul Brabant, Trevan Landin
  • Publication number: 20080017101
    Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.
    Type: Application
    Filed: October 4, 2007
    Publication date: January 24, 2008
    Applicant: ASM America, Inc.
    Inventors: Matthias Bauer, Paul Brabant, Trevan Landin
  • Publication number: 20070224786
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: May 30, 2007
    Publication date: September 27, 2007
    Applicant: ASM AMERICA, INC.
    Inventors: Paul Brabant, Joseph Italiano, Chantal Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20070224787
    Abstract: Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer to be thin and fully relaxed. In some embodiments, a strained layer of Si can be deposited over the fully relaxed SiGe layer.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: Keith Weeks, Paul Brabant
  • Publication number: 20060281322
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: August 18, 2006
    Publication date: December 14, 2006
    Inventors: Paul Brabant, Joseph Italiano, Chantal Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20060234504
    Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.
    Type: Application
    Filed: January 30, 2006
    Publication date: October 19, 2006
    Inventors: Matthias Bauer, Chantal Arena, Ronald Bertram, Pierre Tomasini, Nyles Cody, Paul Brabant, Joseph Italiano, Paul Jacobson, Keith Weeks
  • Publication number: 20060211248
    Abstract: A method for purifying a gas stream in a semiconductor process system comprises cooling impurities in the gas stream. The gas stream may comprise an HCl gas having a moisture content. The moisture contacts a cold element onto which the moisture can condense.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 21, 2006
    Inventors: Paul Brabant, Paul Jacobson, Keith Weeks
  • Publication number: 20060201414
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Application
    Filed: May 12, 2006
    Publication date: September 14, 2006
    Inventors: Paul Brabant, Joe Italiano, Jianqing Wen
  • Publication number: 20060130743
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 22, 2006
    Inventors: Paul Brabant, Joe Italiano, Jianqing Wen
  • Publication number: 20050193952
    Abstract: A substrate support system comprises a relatively thin circular substrate holder having a plurality of passages extending between top and bottom surfaces thereof. The substrate holder includes a single substrate support ledge or a plurality of substrate support spacer vanes configured to support a peripheral portion of the substrate backside so that a thin gap is formed between the substrate and the substrate holder. The vanes can be angled to resist backside deposition of reactant gases as the substrate holder is rotated. A hollow support member provides support to an underside of the substrate holder. The hollow support member is configured to convey gas (e.g., inert gas or cleaning gas) upward into one or more of the passages of the substrate holder. The upwardly conveyed gas flows into the gap between the substrate and the substrate holder.
    Type: Application
    Filed: February 11, 2005
    Publication date: September 8, 2005
    Inventors: Matt Goodman, Jereon Stoutyesdijk, Ravinder Aggarwal, Mike Halpin, Tony Keeton, Mark Hawkins, Lee Haen, Armand Ferro, Paul Brabant, Robert Vyne, Gregory Bartlett, Joseph Italiano, Bob Haro
  • Publication number: 20050191826
    Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.
    Type: Application
    Filed: February 25, 2005
    Publication date: September 1, 2005
    Inventors: Matthia Bauer, Paul Brabant, Trevan Landin
  • Publication number: 20050092235
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 5, 2005
    Inventors: Paul Brabant, Joseph Italiano, Chantal Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20050026400
    Abstract: Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.
    Type: Application
    Filed: June 9, 2004
    Publication date: February 3, 2005
    Inventors: Michael Todd, Paul Brabant, Keith Weeks, Jianqing Wen