Abstract: A system and method of providing real time account information for financial accounts is disclosed. The system includes an event based architecture including an event stream. Financial transaction processing systems publish transaction events to the event stream. A transaction service listening to the event stream detects new transaction events. The transaction service takes action to enrich transaction data. A middleware system reconciles existing transactions and persists transaction records in long term storage. Prior to closing financial accounts, the system can retrieve a list of all scheduled and pending transactions and request that these transactions are canceled before closing the account.

Abstract: Disclosed is a system and method for unsolicited offer management. A communication gateway receives a first structured offer object and selectively communicates the object to a recipient account. In this manner, the operator of the recipient account may selectively control the communication of unsolicited offers.

Abstract: A self-ventilating roofing system that consists of a rigid deck that is connected to the roof support system and has a horizontal opening parallel to the eave, on both slopes, but above the attic space. There is also an opening on either side of the ridge. A radiant barrier comprising of a reflective coating is applied over the roof deck. A slice is made over the lower and upper opening of the deck to allow air to enter the lower opening and exit the upper opening. A panel with vertical grooves is installed over the radiant barrier with the groove side face down. This panel is made of a type of insulated material. A metal drip edge is then installed along the eave. This drip edge should be installed with an air gap between the facia and the drip edge sufficiently wide enough to allow air to enter. A vented ridge vent is then installed at the ridge to allow for the weather proof exit of the air. If a metal roof is being installed then the metal panels can be attached on top of the insulated panel.

Abstract: A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.

Abstract: A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.

Abstract: Disclosed are polypeptides comprising a first segment of continuous amino acids having the sequence AQAGKEPGGSRAHSSHLKSKKGQSTSRHKKLMFKTEGPDSD (SEQ ID NO. 1) covalently linked to a second segment of continuous amino acids having the sequence DSDPGETKFMLKKHRSTSQGKKSKLHSSHARSGGPEKGAQA (SEQ ID NO. 2), or at least two of each covalently linked to each ether. The polypeptides are shown to induce apoptosis of cancer cells that contain mutant p53 or over-expressed wild-type p53.

Abstract: The invention relates to biochemical synthesis of 6-amino caproic acid from 6-aminohex-2-enoic acid compound or from 6-amino-2-hydroxyhexanoic acid, by treatment with an enzyme having ?,?-enoate reductase activity towards molecules containing an ?,?-enoate group and a primary amino group. The invention also relates to processes for obtaining suitable genetically engineered cells for being used in such biotransformation process, and to precursor fermentation of 6-amino caproic acid from intermediates leading to 6-amino caproic acid. Finally, the invention relates to certain novel biochemically produced compounds, namely 6-aminohex-2-enoic acid, 6-aminohexanoic acid, as well as to caprolactam produced therefrom and to nylon-6 and other derivatives produced from such biochemically produced compounds or caprolactam.

Abstract: Disclosed are polypeptides comprising a first segment of continuous amino acids having the sequence AQAGKEPGGSRAHSSHLKSKKGQSTSRHKKLMFKTEGPDSD (SEQ ID NO. 1) covalently linked to a second segment of continuous amino acids having the sequence DSDPGETKFMLKKHRSTSQGKKSKLHSSHARSGGPEKGAQA (SEQ ID NO. 2), or at least two of each covalently linked to each ether. The polypeptides are shown to induce apoptosis of cancer cells that contain mutant p53 or over-expressed wild-type p53.

Abstract: The invention relates to a process for purifying caprolactam, said process comprising (a) subjecting the caprolactam to a hydrogenation by treating the caprolactam with hydrogen in the presence of a heterogeneous nickel containing hydrogenation catalyst, (b) distilling at least a portion of the hydrogenated caprolactam in a distillation column containing nickel in an amount sufficiently low such that ?PANNi?3, wherein ?PANNi=?PAN=?PANNi=0, ?PAN=increase of the PAN number of caprolactam during distilling, ?PANNi=0 increase of the PAN number of caprolactam during distilling under the same conditions in a distillation column free of nickel. Nickel is removed from the caprolactam solution prior to the distillation step.

Abstract: A differential amplifier and method including a differential pair of input MOS transistors coupled to a common tail current source and a pair of MOS load transistors, with the amplifier outputs being disposed intermediate the input and load transistors. Biasing circuitry is included to maintain the load transistors in the linear region of operation. Reset transistors can be used to periodically reset the amplifier by connecting the outputs directly to the inputs.

Abstract: A buffer circuit having voltage clamping capabilities. The buffer circuit includes an input transistor having a gate which receives the input voltage to be buffered and a source connected to a current source. A first clamping transistor has a source connected to the source of the input transistor and a gate which receives a lower clamping voltage. A second clamping transistor is connected intermediate the input transistor and a power supply rail and has a gate for receiving an upper clamping voltage. In one embodiment, the output of the buffer is at the source of the input transistor. In another embodiment, the buffer is implemented as a differential amplifier with the input, first clamping and second clamping transistors being on an input half of the amplifier and the output of the buffer being at the output half.

Abstract: A sample and hold circuit having a single-ended input and a differential output. Switching circuitry operates to couple first and second input capacitors to the single-ended input and to a reference voltage, respectively, when in a sample mode. The switching circuitry also operates in the sample mode to connect a first pair of feedback capacitors between the inputs and outputs of a differential amplifier and to connect a second pair of capacitors between known reference voltages. During the hold mode, the switching circuitry causes the charge present on the input capacitors to be transferred equally to the second pair of feedback capacitors so that the output of the differential amplifier is a differential representation of the single-ended input.

Abstract: An input switch for use in a switch-capacitor circuit having unified architecture, and a switch-capacitor circuit including such an input switch, an amplifier, a capacitor between the amplifier and switch, and at least one NMOS transistor. The input switch samples an input potential in a sampling mode, receives a reference potential, and includes a transmission gate having a first NMOS transistor. The switch is configured to prevent the transmission gate from passing the reference to the capacitor when the reference is so low that the difference between the sampled input and reference is below an overdrive-causing level, thereby preventing capacitor charge loss which would otherwise lead to overdrive while the switch-capacitor circuit compares the reference with the sampled input.

Abstract: An analog-to-digital converting including a resistor network for producing a group of coarse differential reference voltages and a group of fine differential reference voltages, a bank of coarse comparators receiving the coarse differential reference voltage and a bipolar differential input voltage. A bank of fine comparators receives selected ones of the group of fine differential reference voltages, based upon the output of the coarse comparators during a previous clock interval, and a unipolar differential input voltage derived from the bipolar input. Encoder circuitry converts the output of the coarse and fine comparator banks to a digital output.

Abstract: An analog-to-digital converting including a resistor network for producing a group of coarse differential reference voltages and a group of fine differential reference voltages, a bank of coarse comparators receiving the coarse differential reference voltage and a bipolar differential input voltage. A bank of fine comparators receives selected ones of the group of fine differential reference voltages, based upon the output of the coarse comparators during a previous clock interval, and a unipolar differential input voltage derived from the bipolar input. Encoder circuitry converts the output of the coarse and fine comparator banks to a digital output.

Abstract: An interpolating comparator bank having first and second differential amplifiers, each having a differential input and a differential output and first, second and third comparator circuits, each having differential inputs. The differential output of the first differential amplifier and second differential amplifier are coupled to the first and second comparator inputs, respectively. The differential outputs of the first and second differential amplifiers are also both coupled to the differential input of the second comparator circuit. In analog to digital converter circuit applications, the first and second comparators function to provide outputs indicative of the magnitude of a differential input voltage relative to first and third differential reference voltages produced, for example, by a resistor network.

Abstract: A method for maintaining the rotational speed of a crankshaft of an internal combustion engine having a plurality of cylinders each having a spark plug wherein a predetermined amount of delivered fuel is to be combusted at a firing time within each of the plurality of cylinders with each rotation of the camshaft or crankshaft includes the step of operating the internal combustion engine, measuring the rotational speed of the crankshaft, defining an expected engine speed, calculating a speed error as the rotational speed of the crankshaft less the expected engine speed, and changing the predetermined amount of delivered fuel to be combusted in each of the plurality of cylinders to reduce the speed error. The preferred embodiment is implemented in fuzzy logic.