Patents by Inventor Paul Brett

Paul Brett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11151271
    Abstract: A system with an interactive user interface for a plurality of users to author an electronic document simultaneously is described. The system displays visual feedback on the interface to prevent the users from interfering with one another. The system displays data from a remote database linked into the document based on unique identifiers. The data is displayed as an “artifact.” The system monitors and tracks each user's access category level, as well as the access category level of each piece of data pulled from the remote database. The system compares a user's category level to the data from the database to make visible only the portions of the document the user has the appropriate access category level to view and/or modify. The portions of the document that have a higher category level than the user will be hidden from the user either in part or completely. Also, there may be an indicator to the user of such redacted or hidden content from the user's viewer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 19, 2021
    Assignee: PALANTIR TECHNOLOGIES INC.
    Inventors: Paul Thoren, Benjamin Gazzard, David Meiklejohn, Kevin Ng, Matthew Fedderly, Rhys Brett-Bowen
  • Patent number: 11089099
    Abstract: Technologies for managing data object requests in a storage node cluster include a proxy computing node communicatively coupled to the cluster of storage nodes. The proxy computing node is configured to receive data object requests from a communicatively coupled client computing device and identify a plurality of storage nodes of the cluster at which the data object of the data object request is stored. The proxy computing node is further configured to determine which of the identified storage nodes from which to retrieve the stored data object and transmit a request for the data object. Additionally, the proxy computing node is configured to estimate a request completion time based on a service time and a wait time for each of the identified storage nodes, as well as identify which of the storage nodes to retrieve the stored data object from based on the estimated request completion times. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Arun Raghunath, Michael Mesnier, Paul Brett
  • Patent number: 10697563
    Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: June 30, 2020
    Inventor: Paul Brett Wegner
  • Patent number: 10503517
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Publication number: 20190360615
    Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Inventor: Paul Brett Wegner
  • Patent number: 10415724
    Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 17, 2019
    Inventor: Paul Brett Wegner
  • Publication number: 20180060078
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 1, 2018
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V, Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Publication number: 20180017189
    Abstract: An apparatus is disclosed as comprising a first leg of a strut clip; a first rotatable element rotatably attached to the first leg of the strut clip at a first aperture; a second rotatable element rotatably attached to the first leg of the strut clip at the first aperture, where the first and second rotatable elements may have tapered lower edges; a first notch of the first rotatable element may be disposed on a longitudinal edge of the first rotatable element; a second notch of the second rotatable element may be disposed on a longitudinal edge of the second rotatable element; one or more stops may be disposed in the first leg of the strut clip, where the one or more stops may limit rotation of at least one of: the first rotatable element and the second rotatable element; and a first elastic element may be disposed between distal longitudinal edges of the first rotatable element and the second rotatable element.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 18, 2018
    Inventor: Paul Brett Wegner
  • Patent number: 9727345
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russell J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 9672046
    Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, Eugene Gorbatov, Scott D. Hahn, David A. Koufaty, Paul Brett, Abirami Prabhakaran
  • Patent number: 9639372
    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 2, 2017
    Assignee: INTEL CORPORATION
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
  • Publication number: 20170093975
    Abstract: Technologies for managing data object requests in a storage node cluster include a proxy computing node communicatively coupled to the cluster of storage nodes. The proxy computing node is configured to receive data object requests from a communicatively coupled client computing device and identify a plurality of storage nodes of the cluster at which the data object of the data object request is stored. The proxy computing node is further configured to determine which of the identified storage nodes from which to retrieve the stored data object and transmit a request for the data object. Additionally, the proxy computing node is configured to estimate a request completion time based on a service time and a wait time for each of the identified storage nodes, as well as identify which of the storage nodes to retrieve the stored data object from based on the estimated request completion times. Other embodiments are described and claimed.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Inventors: Arun Raghunath, Michael P. Mesnier, Paul Brett
  • Patent number: 9513200
    Abstract: A method for determining a threshold crack length in a machine component including a fatigue crack defining a fatigue crack length and a fatigue crack angle. The method includes determining a component threshold stress intensity factor for the fatigue crack angle, determined from a dataset that includes threshold stress intensity factors for mixed-mode phase angles formed by conducting an asymmetric four point bend test on a test specimen having an initial notch. The method includes determining a threshold crack length based on the component fatigue crack length and fatigue crack angle using a formula disclosed herein.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: December 6, 2016
    Assignee: ROLLS-ROYCE CORPORATION
    Inventors: Jonathan Dubke, Paul Brett Wheelock
  • Patent number: 9448829
    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Gaurav Khanna, Russell J. Fenger, Bryant E. Bigbee, Andrew D. Henroid, David A. Koufaty
  • Patent number: 9329900
    Abstract: A heterogeneous processor architecture is described.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 3, 2016
    Assignee: INTEL CORPORATION
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
  • Patent number: 9166821
    Abstract: In some embodiments, a client computer includes a memory, a client presence program adapted to be located in the memory, and a processor. The processor is coupled to the memory and is adapted to execute the client presence program to receive provider presence information from an instant messaging (IM) server and to store the provider presence information in the memory. The provider presence information includes at least a provider status for at least one service provider.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Robert Knauerhase, Mic Bowman, Paul Brett, Robert Adams
  • Publication number: 20140281457
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Application
    Filed: March 29, 2013
    Publication date: September 18, 2014
    Inventors: Elierzer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Publication number: 20140189302
    Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, David A. Koufaty, Scott D. Hahn, Mishali Naik, Paolo Narvaez, Abirami Prabhakaran, Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Eliezer Weissmann, Paul Brett, Gaurav Khanna, Russell J. Fenger
  • Publication number: 20140189704
    Abstract: A heterogeneous processor architecture is described.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
  • Publication number: 20140189299
    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger