Patents by Inventor Paul Burkley

Paul Burkley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8533827
    Abstract: The present disclosure provides a method for scalable anti-replay windowing. According to one exemplary embodiment, the method may include receiving at least one data packet having at least one new sequence number. The method may also include comparing the at least one new sequence number to an anti-replay window configured to prevent packet replay, the anti-replay window having at least one existing sequence number. The method may further include shifting the contents of the anti-replay window by varying the location of a starting index and an ending index. Of course, additional embodiments, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Paul Burkley, Keith Critchley
  • Publication number: 20120066772
    Abstract: The present disclosure provides a method for scalable anti-replay windowing. According to one exemplary embodiment, the method may include receiving at least one data packet having at least one new sequence number. The method may also include comparing the at least one new sequence number to an anti-replay window configured to prevent packet replay, the anti-replay window having at least one existing sequence number. The method may further include shifting the contents of the anti-replay window by varying the location of a starting index and an ending index. Of course, additional embodiments, variations and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Inventors: Paul Burkley, Keith Critchley
  • Patent number: 8065726
    Abstract: The present disclosure provides a method for scalable anti-replay windowing. According to one exemplary embodiment, the method may include receiving at least one data packet having at least one new sequence number. The method may also include comparing the at least one new sequence number to an anti-replay window configured to prevent packet replay, the anti-replay window having at least one existing sequence number. The method may further include shifting the contents of the anti-replay window by varying the location of a starting index and an ending index. Of course, additional embodiments, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Paul Burkley, Keith Critchley
  • Publication number: 20080288872
    Abstract: The present disclosure provides a method for scalable anti-replay windowing. According to one exemplary embodiment, the method may include receiving at least one data packet having at least one new sequence number. The method may also include comparing the at least one new sequence number to an anti-replay window configured to prevent packet replay, the anti-replay window having at least one existing sequence number. The method may further include shifting the contents of the anti-replay window by varying the location of a starting index and an ending index. Of course, additional embodiments, variations and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 20, 2008
    Applicant: INTEL CORPORATION
    Inventors: Paul Burkley, Keith Critchley
  • Patent number: 7373475
    Abstract: Methods for optimizing memory unit usage to maximize packet throughput for a multiprocessor multithreaded architecture. One method employs a first phase of a software algorithm to allocate data structures to memory units in which the data units are stored and accessed during processing operations. The allocation is such that the data structures are allocated to memory units having lower latencies while satisfying capacity and bandwidth constraints for the memory units. A second phase of the algorithm may be employed to tune the allocation, wherein the performance level of an initial allocation and subsequent reallocations are simulated for an environment in which the memory units and data structures are to be implemented. From the simulation, the allocation providing the best performance level is selected. The simulated environment may include network processor unit (NPU) environments, with the performance level comprising a measure of packet throughput.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Paul Burkley, Prashant Chandra
  • Publication number: 20070005925
    Abstract: Methods for optimizing memory unit usage to maximize packet throughput for a multiprocessor multithreaded architecture. One method employs a first phase of a software algorithm to allocate data structures to memory units in which the data units are stored and accessed during processing operations. The allocation is such that the data structures are allocated to memory units having lower latencies while satisfying capacity and bandwidth constraints for the memory units. A second phase of the algorithm may be employed to tune the allocation, wherein the performance level of an initial allocation and subsequent reallocations are simulated for an environment in which the memory units and data structures are to be implemented. From the simulation, the allocation providing the best performance level is selected. The simulated environment may include network processor unit (NPU) environments, with the performance level comprising a measure of packet throughput.
    Type: Application
    Filed: June 21, 2005
    Publication date: January 4, 2007
    Inventors: Paul Burkley, Prashant Chandra