Abstract: A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

Abstract: A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Abstract: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

Abstract: A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

Abstract: A bus-switch transistor connects two I/O pins when an enable signal on its gate is activated. Each pin has an electro-static-discharge (ESD) protection devices. When the internal ground and the enable are floating, and an ESD pulse is applied between the two pins, an isolation circuit couples part of the ESD pulse to the gate of the bus-switch transistor, keeping the transistor turned off. This forces the ESD pulse to travel through the ESD protection devices, preventing damage to the bus-switch transistor. The isolation circuit has a capacitor between a pin and the gate of a coupling transistor. The capacitor couples the ESD pulse to the gate of the coupling transistor. The coupling transistor turns on, connecting the pin to the gate of a grounding transistor. The grounding transistor then turns on, connecting the gate of the bus-switch transistor to the other pin, which is grounded during the ESD test.

Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Abstract: A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the diode rather than by the programmable transistor itself, programming efficiency no longer depends on the channel length and other parameters of the programmable transistor. The breakdown voltage of the diode is adjusted by varying the lateral spacing between the n+ drain and the p+ diffusion. Smaller lateral spacing enter avalanche breakdown at lower voltages and thus program the programmable transistor at a lower drain voltage.

Abstract: A process for manufacturing an integrated circuit having both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides. The polycide film is patterned such that a protective structure of gate material is formed on top the base region while the gate of the FET is formed, in a single process step. Ionic species are implanted to form the source and drain and the collector contact. The protective structure of gate material in the active region of the bipolar transistor is removed just before the base region is implanted to form the base. In a second embodiment, a silicon nitride oxidation mask for field oxide regions is formed over the bipolar transistor and the field effect transistor active regions. The portion of the nitride oxidation mask is removed only from the FET active regions after field oxide regions are formed.

Abstract: A process for manufacturing both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides on the surface of the semiconductor substrate is patterned such that a protective structure of gate material is formed on top the base region of the bipolar transistor while the gate of the FET is formed. The channel region of the FET is defined by the gate, which also serves as a mask for etching away the gate oxide from the source and drain regions. The protective structure of gate material in the active region of the bipolar transistor is removed just before implantation to form the base of the bipolar transistor. In a second embodiment a silicon nitride oxidation mask for formation of filed oxide regions over the bipolar transistor and the FET active regions is formed and portions of the nitride oxidation mask is removed only from the FET active regions after field oxide regions are formed.