Abstract: Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.

Abstract: An electronic design automation (EDA) tool to validate representations of a design is disclosed. Reference and compared representations of the design are intended to respond to stimulus in the same way, but at different levels of abstraction. The reference and compared representations are simulated, at some point, to each generate waveform signals and measured results. Simulation can be with the same tool or different tools. The same or different testbench can be used on the reference and compared representations in the simulation. A design representation validation function compares the two sets of generated waveform signals and compares the two sets of measured results to identify any violations. The measured results and/or waveform signals could be loaded from previous simulations and just validated within the validation tool.

Abstract: A method and system for template-based behavioral model creation for behavioral modeling is disclosed. A design characterization and modeling (DCM) tool has a number of templates for different circuits. A designer chooses a template and customizes the template with a number of parameters and optionally pin assignments. The DCM tool generates a behavioral model that has real wire (“Wreal”) capability. The transistor level design is simulated with a testbench according to the parameters to generate Wreal calibration information. The behavioral model uses the Wreal calibration information in behavioral modeling to provide quick behavioral processing of the behavioral model with the benefit of increased accuracy provided by the Wreal calibration information, for example. Optionally, the DCM tool generates another testbench that validates the analog and behavioral models.

Abstract: A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses on an ‘as and when required’ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task, the system checks-out a burst license for use in processing the task, and assigns the license to a particular CPU. The task is then performed at that CPU, and once completed the burst license is returned to the license pool.

Abstract: A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses on an ‘as and when required’ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task, the system checks-out a burst license for use in processing the task, and assigns the license to a particular CPU. The task is then performed at that CPU, and once completed the burst license is returned to the license pool.

Abstract: A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses on an ‘as and when required’ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task, the system checks-out a burst license for use in processing the task, and assigns the license to a particular CPU. The task is then performed at that CPU, and once completed the burst license is returned to the license pool.

Abstract: In one aspect, the present invention provides a system for determining the operation of an integrated circuit, comprising:receiving means (4,5) for receiving and storing information about said integrated circuit and for pre-storing a range of stimuli to be applied to a model of said integrated circuit;selecting means (6) for selecting at least one stimulus from said range;a first translator (8) for translating said selected stimulus from a reference language into an alien language;an alien simulator (12) for applying said translated stimulus to an alien model of said integrated circuit and obtaining a response to said translated stimulus;a second translator (14) for translating the said response from said alien language to said reference language; andstore means (16) for storing said translated response, said stimulus and response portraying operation of the integrated circuit.