Patents by Inventor Paul C. Serra

Paul C. Serra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for electronics timing delay calibration
    Patent number: 11067630
    Abstract: A system and method for measuring or calibrating a delay through a circuit path within an integrated circuit is disclosed. In some embodiments, a delay locked loop (DLL) circuit is provided. An arbiter circuit in the DLL compares timing of a clock signal and a delayed version of the clock signal that has passed through the circuit path. The percentage of the clock signal with feature that arrives before the corresponding feature of the delayed clock can be an indication of the delay timing through the path relative to a period of the clock signal and used as feedback in the DLL.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: July 20, 2021
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: John Conklin, Paul C. Serra
  • SYSTEM AND METHOD FOR ELECTRONICS TIMING DELAY CALIBRATION
    Publication number: 20200292616
    Abstract: A system and method for measuring or calibrating a delay through a circuit path within an integrated circuit is disclosed. In some embodiments, a delay locked loop (DLL) circuit is provided. An arbiter circuit in the DLL compares timing of a clock signal and a delayed version of the clock signal that has passed through the circuit path. The percentage of the clock signal with feature that arrives before the corresponding feature of the delayed clock can be an indication of the delay timing through the path relative to a period of the clock signal and used as feedback in the DLL.
    Type: Application
    Filed: April 21, 2017
    Publication date: September 17, 2020
    Inventors: John Conklin, Paul C. Serra