Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

Abstract: A test module for testing the susceptibility of an integrated circuit design to latch-up, the test module comprising a plurality of test blocks (30), connected in parallel, each test block (30) comprising an injector block (12) for applying a stress current or voltage to the respective test block (30), and a plurality of sensor blocks (13) located at successively increasing distances from the respective injector block (12), each sensor block (13) comprising a PNPN latch-up test structure. The present invention combines the respective advantages of conventional IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.