Patents by Inventor Paul Caprioli

Paul Caprioli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INDEX GENERATION FOR CACHE MEMORIES
    Publication number: 20120166756
    Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 28, 2012
    Applicant: Oracle International Corporation
    Inventors: Paul Caprioli, Martin Karlsson, Shailender Chaudhry
  • Unified cache structure that facilitates accessing translation table entries
    Patent number: 8185692
    Abstract: One embodiment provides a system that includes a processor with a unified cache structure that facilitates accessing translation table entries (TTEs). This unified cache structure can simultaneously store program instructions, program data, and TTEs. During a memory access, the system receives a virtual memory address. The system then uses this virtual memory address to identify one or more cache lines in the unified cache structure which are associated with the virtual memory address. Next, the system compares a tag portion of the virtual memory address with the tags for the identified cache line(s) to identify a cache line that matches the virtual memory address. The system then loads a translation table entry that corresponds to the virtual memory address from the identified cache line.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: May 22, 2012
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Gregory M. Wright
  • Merging checkpoints in an execute-ahead processor
    Patent number: 8181002
    Abstract: One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode. The system then generates a first checkpoint and a second checkpoint during the speculative-execution episode. Next, the system merges the first checkpoint with the second checkpoint during the speculative-execution episode, wherein merging the first and second checkpoints conserves processor resources.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: May 15, 2012
    Assignee: Oracle America, Inc.
    Inventors: Sherman H. Yip, Paul Caprioli, Marc Tremblay
  • Method and apparatus for programmatically rewinding a register inside a transaction
    Patent number: 8161273
    Abstract: Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving a pre-transactional state of registers in a first register file. The system then allocates one or more registers for temporary use during the transaction. Upon finishing using each allocated register during the transaction, the system executes an instruction that restores the allocated register to the pre-transactional state.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 17, 2012
    Assignee: Oracle America, Inc.
    Inventor: Paul Caprioli
  • Using address and non-address information for improved index generation for cache memories
    Patent number: 8151084
    Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: April 3, 2012
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Martin Karlsson, Shailender Chaudhry
  • Method and apparatus for determining cache storage locations based on latency requirements
    Patent number: 8065485
    Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: November 22, 2011
    Assignee: Oracle America, Inc.
    Inventors: Gideon N. Levinsky, Paul Caprioli, Sherman H. Yip
  • Method and apparatus for improving transactional memory commit latency
    Patent number: 8041900
    Abstract: Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 18, 2011
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Martin Karlsson, Sherman H. Yip
  • SPACE-EFFICIENT MECHANISM TO SUPPORT ADDITIONAL SCOUTING IN A PROCESSOR USING CHECKPOINTS
    Publication number: 20110167243
    Abstract: Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were calculated during scouting mode. These forwarded results may be used during scouting mode to calculate memory load addresses for yet other in-flight instructions, and the processor may accordingly cause data to be prefetched from these calculated memory load addresses. The set of register storage locations may comprise a working register file or an active portion of a multiported register file.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 7, 2011
    Inventors: Sherman H. Yip, Paul Caprioli
  • Aggressive store merging in a processor that supports checkpointing
    Patent number: 7934080
    Abstract: Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: April 26, 2011
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Martin Karlsson, Gideon N. Levinsky, Khondakar A. Mujtaba, Shailender Chaudhry, Murali K. Inaganti
  • Method and apparatus for synchronizing threads on a processor that supports transactional memory
    Patent number: 7930695
    Abstract: One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: April 19, 2011
    Assignee: Oracle America, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay, Paul Caprioli
  • Method and apparatus for recovering from branch misprediction
    Patent number: 7890739
    Abstract: Embodiments of the present invention provide a system that executes a branch instruction. When executing the branch instruction, the system obtains a stored prediction of a resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction. If an actual resolution of the branch instruction is different from the predicted resolution (i.e., if the branch is mispredicted), the system updates the stored prediction of the resolution of the branch instruction to the actual resolution of the branch instruction. The system then re-executes the branch instruction. When re-executing the branch instruction, the system obtains the stored prediction of the resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: February 15, 2011
    Assignee: Oracle America, Inc.
    Inventor: Paul Caprioli
  • METHOD AND APPARATUS FOR DETERMINING CACHE STORAGE LOCATIONS BASED ON LATENCY REQUIREMENTS
    Publication number: 20100299482
    Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.
    Type: Application
    Filed: May 22, 2009
    Publication date: November 25, 2010
    Inventors: Gideon N. Levinsky, Paul Caprioli, Sherman H. Yip
  • Return address stack recovery in a speculative execution computing apparatus
    Patent number: 7836290
    Abstract: A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: November 16, 2010
    Assignee: Oracle America, Inc.
    Inventors: Shailender Chaudhry, Quinn A. Jacobson, Paul Caprioli, Marc Tremblay
  • UNIFIED CACHE STRUCTURE THAT FACILITATES ACCESSING TRANSLATION TABLE ENTRIES
    Publication number: 20100205344
    Abstract: One embodiment provides a system that includes a processor with a unified cache structure that facilitates accessing translation table entries (TTEs). This unified cache structure can simultaneously store program instructions, program data, and TTEs. During a memory access, the system receives a virtual memory address. The system then uses this virtual memory address to identify one or more cache lines in the unified cache structure which are associated with the virtual memory address. Next, the system compares a tag portion of the virtual memory address with the tags for the identified cache line(s) to identify a cache line that matches the virtual memory address. The system then loads a translation table entry that corresponds to the virtual memory address from the identified cache line.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Paul Caprioli, Gregory M. Wright
  • MECHANISM FOR INCREASING THE EFFECTIVE CAPACITY OF THE WORKING REGISTER FILE
    Publication number: 20100180103
    Abstract: A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 15, 2010
    Inventors: Shailender Chaudhry, Paul Caprioli, Marc Tremblay
  • Method and apparatus for measuring performance during speculative execution
    Patent number: 7757068
    Abstract: One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: July 13, 2010
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Shailender Chaudhry, Sherman H. Yip
  • SEMI-ABSOLUTE BRANCH INSTRUCTIONS FOR EFFICIENT COMPUTERS
    Publication number: 20100161950
    Abstract: Apparatus and methods are disclosed for a computation processor that can execute a semi-absolute branch instruction, as well as methods of operation and of generating the semi-absolute branch instruction.
    Type: Application
    Filed: December 24, 2008
    Publication date: June 24, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Paul Caprioli, Peter B. Kessler, Christopher A. Vick
  • Method and apparatus for counting instructions during speculative execution
    Patent number: 7716457
    Abstract: One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: May 11, 2010
    Assignee: Oracle America, Inc.
    Inventors: Paul Caprioli, Shailender Chaudhry, Sherman H. Yip
  • Method and apparatus for selectively prefetching based on resource availability
    Patent number: 7707359
    Abstract: One embodiment of the present invention provides a system which facilitates selective prefetching based on resource availability. During operation, the system executes instructions in a processor. While executing the instructions, the system monitors the availability of one or more system resources and dynamically adjusts an availability indicator for each system resource based on the current availability of the system resource. Upon encountering a prefetch instruction which involves the system resource, the system checks the availability indicator. If the availability indicator indicates that the system resource is not sufficiently available, the system terminates the execution of the prefetch instruction, whereby terminating execution prevents prefetch instructions from overwhelming the system resource.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 27, 2010
    Assignee: Oracle America, Inc.
    Inventors: Wayne Mesard, Paul Caprioli
  • Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
    Patent number: 7689813
    Abstract: Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: March 30, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Paul Caprioli, Shailender Chaudhry, Marc Tremblay