Abstract: A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.

Abstract: A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

Abstract: A method and system in a data processing system are disclosed for efficiently handling exceptions. The data processing system includes a register for storing indications of multiple instructions while the multiple instructions are being concurrently processed. An exception is generated within the data processing system. A determination is made whether the exception was generated by one of the multiple instructions. In response to a determination that one of the multiple instructions generated the exception, a determination is then made whether an indication of the instruction which generated the exception is stored in a particular position within a register within the data processing system. In response to a determination that the indication of the instruction is stored in the particular position within the register, the exception is associated with a first priority group.

Abstract: A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An array is established having multiple entry fields for storing multiple entries. Each of the multiple entry fields is associated with a different one of the plurality of registers. A status of each of the plurality of registers is determined. A plurality of partitions are established within the array. Each of the partitions are concurrently accessible by the data processing system. A plurality of the multiple entry fields are associated with one of the plurality partitions. An entry is stored in each of the multiple entry field. The entry includes the status of each of the plurality of registers. Each entry is associated with one of the partitions so that a plurality of the multiple entries may be concurrently accessed.

Abstract: A cache memory uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. In a semi-associative instruction cache, with the CAM and eight cache lines grouped together to form camlets, a binary index is used to address one camlet in the cache array, and the effective address tag match is used to select a potential line within the camlet in accessing data stored in the cache array. Since an E-tag match causes that cache line's wordline to activate, proper cache operation requires that no two (or more) E-tags within a camlet have the same match criteria (ECAM entry); the invalidation of entries is done to prevent this from happening. Due to the mapping of the effective address into the E-tag CAM and the camlet binary index, addresses that are 1-Meg apart point to the same camlet and have the same ECAM tag. The method thus employs a semi-associative cache having cache lines configured in camlets of, for example, eight lines per camlet.