Abstract: A computer-implemented method for validation of a software product via a distributed computing infrastructure includes receiving configuration data for a plurality of validation tasks of the validation, receiving code data representative of the software product, defining a validation pipeline to implement the plurality of validation tasks based on the configuration data, and initiating execution of the plurality of validation tasks on a plurality of virtual machines of the distributed computing infrastructure. Initiating the execution includes sending the code data and data indicative of the defined validation pipeline to configure each virtual machine in accordance with the code data and the defined validation pipeline.

Abstract: A display method includes: detecting objects by sensor array; utilizing an environment reconstruction unit for receiving sensing information from the sensor array and perform a reconstruction process based on the sensing information and transforming the latter into object coordinate based on user-chosen mode; and utilizing a display device to display an iconized environment video or scene resulted by integrating an indicative icon of the object with the object coordinate.

Abstract: A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

Abstract: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

Abstract: An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.

Abstract: A video decoder having an input buffer for receiving an encoded and compressed data stream, parsing circuitry for removing header information from said data stream, circuitry for decoding said data stream, circuitry for decompressing said data stream, circuitry for selecting predetermined portions of preselected frames, memory for storing said decompressed data stream and selected portions of said preselected frames, and circuitry for reconstructing selected portions of said preselected frames is provided.

Abstract: A programmable multimedia accelerator which maximizes data bandwidth utilization with minimal hardware (and consequently minimal power consumption) is provided herein. In one embodiment, the accelerator includes four functional units, a routing unit, and a control module. The functional units each operate on four input bytes and a carry-in bit, and produce two output bytes and a carry-out bit. The carry-out bit of each functional unit is provided as a carry-in bit to another functional unit, allowing the functional units to operate cooperatively to carry out extended-precision operations when needed. The functional units can also operate individually to perform low-precision operations in parallel. The routing unit is coupled to the functional units to receive the output bytes and to provide a permutation of the output bytes as additional pairs of input bytes to the functional units.

Abstract: A decoded video signal which was encoded in accordance with a standard, such as MPEG-2, is encoded "on the fly" using a lossless linear predicted coding technique and stored in a compressed form in a RAM. A separate encoding technique is provided for B pictures and for I or P pictures. The compressed B pictures are decompressed for display. The compressed I or P pictures are decompressed for display or for use in decoding other P or B pictures.