Abstract: An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of the array having excessive leakage, thereby identifying and repairing latent defects that may become a cause of failure.

Abstract: An integrated circuit having a charge pump is tested for excessive current draw by counting the number of times the charge pump cycles in a test interval, storing the result in a register that is used for another purpose during operation and comparing the result with a reference number representing acceptable leakage, thereby identifying latent defects that may become a cause of failure as well as short circuits.

Abstract: An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of the array having excessive leakage, thereby identifying and repairing latent defects that may become a cause of failure.

Abstract: An integrated circuit having a charge pump is tested for excessive current draw by counting the number of times the charge pump cycles in a test interval, storing the result in a register that is used for another purpose during operation and comparing the result with a reference number representing acceptable leakage, thereby identifying latent defects that may become a cause of failure as well as short circuits.

Abstract: The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

Abstract: The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.