Patents by Inventor Paul Coelho

Paul Coelho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Use of cache to reduce memory bandwidth pressure with processing pipeline
    Patent number: 9116814
    Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: August 25, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Jeffrey G. Libby, Anurag P. Gupta, Paul Coelho
  • Use of cache to reduce memory bandwidth pressure with processing pipeline
    Patent number: 8627007
    Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 7, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Jeffrey G. Libby, Anurag P. Gupta, Paul Coelho