Patents by Inventor Paul Coene

Paul Coene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9117310
    Abstract: A virtual camera system comprises a plurality of physical cameras and a hardware setup miming software to create virtual viewpoints for the virtual camera system. The position of the physical cameras is constrained, where the main constraint is the overlap between the physical cameras. The present invention provides a method for creating a virtual viewpoint of a plurality of images captured by the plurality of cameras, the images comprising current frames and previous frames.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: August 25, 2015
    Assignee: IMEC
    Inventors: Paul Coene, Johan De Geyter, Eddy De Greef, Bert Geelen, Bart Masschelein, Geert Vanmeerbeeck, Wilfried Verachtert
  • Patent number: 9038072
    Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: May 19, 2015
    Assignee: XILINX, INC.
    Inventors: Vincent Nollet, Paul Coene, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest, Theodore Marescaux, Andrei Bartic
  • Publication number: 20130016097
    Abstract: A virtual camera system comprises a plurality of physical cameras and a hardware setup miming software to create virtual viewpoints for the virtual camera system. The position of the physical cameras is constrained, where the main constraint is the overlap between the physical cameras. The present invention provides a method for creating a virtual viewpoint of a plurality of images captured by the plurality of cameras, the images comprising current frames and previous frames.
    Type: Application
    Filed: April 1, 2011
    Publication date: January 17, 2013
    Applicant: IMEC
    Inventors: Paul Coene, Johan De Geyter, Eddy De Greef, Bert Geelen, Bart Masschelein, Geert Vanmeerbeeck, Wilfried Verachtert
  • Patent number: 8020163
    Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: September 13, 2011
    Assignees: Interuniversitair Microelektronica Centrum (IMEC), Xilinx, Inc.
    Inventors: Vincent Nollet, Paul Coene, Theodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest
  • Patent number: 7904848
    Abstract: A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processing units disposed on a layer permitting interconnection between connection nodes; and a mapping unit adapted to substantially simultaneously optimize placement of the tasks on the plurality of programmable processing units and routing of interconnections between the plurality of processing units, the mapping unit adapted to select one placement algorithm among a plurality of predetermined placement algorithms and to select one routing algorithm from a plurality of predetermined placement algorithms, the selection configured to prefer use of non-random algorithms.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: March 8, 2011
    Assignees: IMEC, Fujitsu Ltd.
    Inventors: Paul Coene, Hisanori Fujisawa
  • Publication number: 20090187756
    Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.
    Type: Application
    Filed: December 10, 2008
    Publication date: July 23, 2009
    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
    Inventors: Vincent Nollet, Paul Coene, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest, Theodore Marescaux, Andrei Bartic
  • Publication number: 20070220522
    Abstract: A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processing units disposed on a layer permitting interconnection between connection nodes; and a mapping unit adapted to substantially simultaneously optimize placement of the tasks on the plurality of programmable processing units and routing of interconnections between the plurality of processing units, the mapping unit adapted to select one placement algorithm among a plurality of predetermined placement algorithms and to select one routing algorithm from a plurality of predetermined placement algorithms, the selection configured to prefer use of non-random algorithms.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 20, 2007
    Inventors: Paul Coene, Hisanorj Fujisawa
  • Publication number: 20050203988
    Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).
    Type: Application
    Filed: November 24, 2004
    Publication date: September 15, 2005
    Inventors: Vincent Nollet, Paul Coene, Theodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest
  • Publication number: 20040049672
    Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.
    Type: Application
    Filed: June 2, 2003
    Publication date: March 11, 2004
    Inventors: Vincent Nollet, Paul Coene, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest, Theodore Marescaux, Andrei Bartic