Abstract: A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and terminating access when the program leaves the loop.

Abstract: A method and system for prefetching data from storage and storing the data in a cache memory for use by an executing program includes means for detecting when a program has entered a processing loop and has completed at least one pass through the processing loop. At the completion of one pass through the processing loop, determining the requirement for additional data and prefetching the required data. Monitoring the operation of the program to detect termination of loop processing and terminating the prefetch of data from storage until the detection of a subsequent program loop.

Abstract: A computer system having interrupts synchronized to data storage by having an interrupt data signal (interrupt packet) follow the path of the data to an interrupt receiver, which interrupts the processor to execute an interrupt service routine. Rather than having a dedicated interrupt line from a peripheral device to a processor, the peripheral device sends the interrupt across a bus from the peripheral to the processing unit via an interrupt receiver.

Abstract: A computer system having interrupts synchronized to data storage by having an interrupt data signal (interrupt packet) follow the path of the data to an interrupt receiver, which interrupts the processor to execute an interrupt service routine. Rather than having a dedicated interrupt line from a peripheral device to a processor, the peripheral device sends the interrupt across a bus from the peripheral to the processing unit via an interrupt receiver.