Patents by Inventor Paul D. Asetta

Paul D. Asetta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5273615
    Abstract: An apparatus (60) which handles fragile semiconductor wafers (21) adhesively mounted to a submount (22) using a high temperature wax is provided. The apparatus (60) includes a vacuum chuck (24) for holding a first surface of the wafer (21) and a solvent chamber (11, 11') for applying solvent to the back surface of the submount (22). The apparatus (60) includes an enclosure (29) for providing an inert gas environment around the solvent chamber (11, 11'), the wafer (21), and the vacuum chuck (24). The apparatus (60) further includes a means for remounting (30) the wafer (21) to a submount (22) using a low temperature wax after the high temperature wax is dissolved. The wafer (21) is then released from the vacuum chuck (24) and the first surface of the wafer (21) is mounted to an adhesive tape (34). Following the mounting, the low temperature wax is dissolved or melted to demount the wafer (21 ) from the submount (22), leaving the wafer (21) securely mounted on the adhesive tape (34) for sawing.
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: December 28, 1993
    Assignee: Motorola, Inc.
    Inventors: Paul D. Asetta, Lawrence R. Gardner, Michael P. Norman
  • Patent number: 5256599
    Abstract: A wax (13) dissolved in solvent is placed on a semiconductor wafer (12) and made uniform. An assembly is formed by bonding the semiconductor wafer (12) to a submount (17) with a uniform wax layer (14). The submount (17) supports and allows handling of the semiconductor wafer (12) during wafer process steps. The assembly is heated in a vacuum to remove solvent and air trapped in the uniform wax layer (14) thereby minimizing air voids which can cause a non-uniform bond. The assembly is then annealed to reduce stress on the semiconductor wafer (12) induced by differing material thermal expansion rates of the semiconductor wafer (12), the uniform wax layer (14), and the submount (17).
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: October 26, 1993
    Assignee: Motorola, Inc.
    Inventors: Paul D. Asetta, Rajiv Bajaj, Lawrence R. Gardner, Michael P. Norman, James J. Wang