Abstract: A laminate substrate may include a slug positioned within a cavity of a laminate core. The laminate substrate may have routing layers on either side of the laminate core, at least one of which is coplanar with an outer side of the slug. A capping layer may then be applied to the laminate substrate which is directly coupled with the slug and the routing layer. In embodiments, a dielectric layer may be coupled with the capping layer, and an additional routing layer may be coupled with the dielectric layer. Therefore, the routing layer may be an “inner” routing layer that is coplanar with, and coupled with, the slug.

Abstract: A laminate substrate may include a slug positioned within a cavity of a laminate core. The laminate substrate may have routing layers on either side of the laminate core, at least one of which is coplanar with an outer side of the slug. A capping layer may then be applied to the laminate substrate which is directly coupled with the slug and the routing layer. In embodiments, a dielectric layer may be coupled with the capping layer, and an additional routing layer may be coupled with the dielectric layer. Therefore, the routing layer may be an “inner” routing layer that is coplanar with, and coupled with, the slug.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of thermal via structures with surface features. In some embodiments the surface features may have dimensions greater than approximately one micron. The thermal via structures may be incorporated into a substrate of an integrated circuit device. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.