Patents by Inventor Paul D. Cassity

Paul D. Cassity has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6884717
    Abstract: An etching based semiconductor wafer thinning arrangement usable as an improved alternative to the usual grinding and polishing wafer thinning. The thinned wafer includes a structurally enhancing wafer backside grid array of original wafer thickness semiconductor material with grid cells surrounding individual thinned wafer areas and serving to improve the strength and physical rigidity characteristics of the thinned wafer. Preferably this grid array is supplemented with an additional, wafer periphery-located, backside ring of semiconductor material also of original wafer thickness. Ability to avoid a wafer front side mounting during thinning accomplishment, fast etching, reduced wafer breakage, enhanced wafer strength and improved wafer handling achieved with the disclosed thinning arrangement all contribute to achieved advantages over conventional wafer thinning.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: April 26, 2005
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Gregory C. Desalvo, Tony K. Quach, John L. Ebel, Anders P. Walker, Paul D. Cassity