Abstract: A source (20) provides an input signal (S1) to be phase shifted and a combining circuit (24) concurrently combines first (A), second (B) and third (C) intermediate signals derived from the input signal (S1), and having differing phase shifts (0, −45, +135 deg), to form a phase shifted output signal (S2). A first amplitude controller (34, 38, 30, 32), responsive to a phase control signal (S3) supplied thereto, varies the amplitudes of the second (B) and third (C) intermediate signals in opposite directions (38) for controlling the phase of the phase shifted output signal. Additionally, a further amplitude controller (40, 42) is provided for reducing a tendency for variations in the phase shift control signal (S3) to alter the amplitude of alternating current (FIG. 5) and direct current (FIG. 6) components of the phase shifted output signal (S2).

Abstract: A video control system, comprises a deflection system having a dimensionally adjustable raster, a circuit for detecting a letterbox video signal source and a circuit for dimensionally controlling the raster of the deflection system responsive to the detecting circuit. The detecting circuit and the control circuit are operable automatically. The detection circuit can comprise a circuit for measuring video luma levels of the video signal source in at least two regions of each video field and a circuit for comparing the luma levels from each of the regions to respective threshold levels. In an alternative, the detection circuit comprises a circuit for comparing respective minimum and maximum luminance values for a plurality of successive video lines, a circuit for storing minimum and maximum luminance values for the plurality of video lines, a circuit for generating gradients indicative of the stored values and a circuit for comparing the gradients to threshold values.

Abstract: Read column conductors and write column conductors of a memory array are addressed by respective triggerable sequential pulse generators which, upon receiving respective trigger pulses, provide respective read and write address pulses to respective column conductors of the array. Data to be stored is written in parallel to cells of the memory a column at a time at a rate determined by the write sequential pulse generator and is recovered a column at a time at a rate determined by the read sequential pulse generator. Advantageously, (1) the ratio of the read and write rates may be selected to provide time compression, time expansion or constant delay of video data; (2) additionally data may be written and read concurrently without bus contention and (3) addressing is simplified by a timed application of trigger pulses to the pulse generators whereby there is no need for application to the memory of binary addressing data.

Abstract: A charge pump arrangement receives a digital error word representing an error signal and charges or discharges a capacitor in accordance with the sign of the error word by an amount that is proportional to the absolute value of the error word. The voltage produced in the capacitor is coupled to a frequency control terminal of a voltage controlled crystal oscillator that is used in, for example, a stereo decoder.

Abstract: A controlled crystal oscillator of a stereo decoder of a television receiver using CMOS technology includes first, second and third differential emplifiers that produce corresponding first, second and third pairs of anti-phase output signals. The first and second differential amplifiers have variable gains that vary in opposing manners in accordance with a frequency control signal. The oscillatory signal of a crystal is coupled to corresponding input terminals of the three differential amplifiers such that the phase of the signal that is developed at the input terminal of the third differential amplifier is phase-shifted by approximately 90.degree. relative to those developed at the input terminals of the other two amplifiers. The three pairs of output signals are combined to form a single-ended oscillatory signal that is coupled back to the crystal to complete a regulative feedback path. The frequency of oscillation is determined in accordance with the frequency control signal.

Abstract: A MOSFET analog signal squaring circuit is disclosed. A first MOSFET has a source electrode coupled to a bias voltage source, a gate electrode coupled to an input terminal, and a drain electrode coupled to an output terminal. A signal inverter is also coupled to the input terminal. A second MOSFET has a source electrode coupled to the bias voltage source, gate electrode coupled to the signal inverter, and a drain electrode coupled to the output terminal. A load impedance is coupled between the output terminal and a supply voltage source.

Abstract: A regulating power supply for a video display apparatus includes a switching transistor that periodically energizes a transformer winding. Input switching pulses for the transistor are varied in width and frequency to optimize power transfer via the transformer. The charge and discharge rates of a capacitor determine the pulse width and frequency. The capacitor charging current is selectively switched to be connected to the capacitor while the capacitor discharge current is controlled in response to a feedback signal derived from the regulated voltage level.

Abstract: A television receiver is arranged to selectively display either information from a broadcast television signal, or information from an auxiliary video signal. The black image reference level associated with the broadcast signal information is sampled and used to automatically establish the black image reference level of the auxiliary video signal.

Abstract: A television receiver is arranged to selectively display either information from a broadcast television signal or information from an auxiliary video signal, in accordance with the position of a switching network to which the signals are capacitively coupled via respective capacitors. Similar black reference levels are established for the television and auxiliary signals by means of respective clamping circuits, including the coupling capacitors, which operate at different times but with respect to the same clamping reference voltage.

Abstract: A teletext decoder extracts digital information from a video signal for displaying graphics and textual information embedded in the video signal. The decoder includes a prefix processor responding to user supplied commands for selecting and storing the pertinent embedded information. The decoder includes a common memory for storing the digital words provided by the prefix processor and a microcomputer capable of reading from and writing to the common memory. The microcomputer reads the data provided by the prefix processor, converts it to digital words representing the picture elements and stores the converted digital words in the common memory. The decoder includes a display processor which reads the converted digital words from the common memory to drive an image display device.

Abstract: A teletext decoder extracts digital information from a video signal for displaying graphics and textual information embedded in the video signal. The decoder includes a prefix processor responding to user supplied commands for selecting and storing the pertinent embedded information into a memory. The microcomputer reads the data provided by the prefix processor, converts it to pixel words representing picture elements and restores the converted data into the memory. The decoder includes a display processor which reads more than one pixel word at a time when accessing the memory, and translates each pixel word to 3 groups of color codes and to a one-bit transparency code.

Abstract: First and second transistors of the same conductivity type have their emitter-collector paths serially disposed across a DC operating potential source, with the emitter electrode of the first transistor directly connected to the collector electrode of the second transistor and to an output terminal. First and second emitter-followers have inputs commonly connected via a resistor to a reference point. The output of the first emitter-follower directly drives the base electrode of the first transistor, while the base electrode of the second transistor is rendered responsive to the output of the second emitter-follower. A control transistor is commonly connected to the inputs of the emitter-followers so as to disable said emitter-followers and render both of said first and second transitors non-conductive when said control transistor is conducting, and to enable said emitter-followers and render both of said first and second transistors conducting when control transistor is cut off.

Abstract: Apparatus is described for converting the digital output of a microprocessor system into a video signal. The video signal is thereafter applied to a television receiver to cause objects described and controlled by a microprocessor system to be displayed on the television receiver. The apparatus is specifically used to provide an interface between a microprocessor controlled video game and a television monitor or receiver.

Abstract: Method and apparatus for serial data transmission wherein each data word has a fixed bit length and each bit is transmitted during a fixed duration data period following a sync pulse. The sync pulse for each data word has a duration equal to a data period. Each data bit pulse has a duration less than a data period. The method and apparatus is particularly suitable for remote control systems for use with television receivers.