Abstract: DC transients are removed from a digital filter such as a sigma delta filter (in particular from a sigma delta high pass filter) from the outset by presetting an input summing node to a sigma delta modulator. While the input summing node may be preset using any appropriate input, in a disclosed embodiment, a sigma delta high pass filter is preset by switching a partial feedback term between an input containing the non-zero preset value and the normal input comprising the output from the input summing node. The preset value is chosen based on the value of the zero of the transfer function of the sigma delta high pass filter, e.g., with the complement of the gain factor.

Abstract: The present invention provides a digital pre-distortion filter in arrangement with a data access arrangement (DAA) on the component side (e.g., in a modem chipset). This arrangement of the pre-distortion filter outside of the DAA allows digital processes such as digital emulation of the central office impedance to remain unaffected by the pre-distortion in the transmitted signal, allowing the dynamic range of the transmitted signal to be flattened to minimize return loss without complicating the transfer function of the digital emulation of the central office complex load. In the case of a digital emulation filter, placement of a digital pre-distortion filter outside of an analog-to-digital (A/D) digital-to-analog (D/A) loop also minimizes the noise otherwise associated with the use of a pre-distortion filter. Thus, benefits of a pre-distortion filter can be gained without interfering with emulation of impedance, and without causing a significant amount of noise in the transmitted signal.

Abstract: An AC impedance matching architecture which provides programmable AC impedance matching in a given range using a digital filter to filter a signal fed back from the impedance matched line to generate an AC impedance emulation control signal. The AC impedance emulation control signal is combined with a transmit signal (if desired) and drives a voltage controlled current source, which is in parallel with a reference impedance. A voltage is developed across the reference impedance to drive, e.g., the telephone line. The reference impedance is chosen based on a desired maximum AC impedance. The gain of the digital filter, a first order sigma delta filter in the disclosed embodiment, is chosen based on the desired value of the AC impedance. The transfer function of the digital filter is derived based on a desired AC impedance.

Abstract: A 2nd order digital filter requiring only one sigma delta modulator is created by implementing (1) a 2nd order feedforward term created by the cascade of two 1st order elements; (2) a 2nd order feedback term created by the cascade of two 1st order elements; and (3) another 2nd order feedback term created by the cascade of two more 1st order elements to eliminate the need for another sigma delta modulator to provide a 2nd order filter. Thus, for the mere ‘cost’ of additional feedback loops, which are small in comparison with the size and complexity of another sigma delta modulator, a second sigma delta modulator is not necessary to implement a 2nd order digital filter in accordance with the principles with the present invention.

Abstract: A scalable overflow clamp for controlling the level of allowable digital signal overflow in a gain scaler/summer having an initial full-scale range and a feedback path for establishing a feedback gain. The clamp includes a range scaler for determining the feedback gain and generating a modified full-scale range relative to the feedback gain. The modified full-scale range defines a substantially constant overflow capability relative to the feedback gain. An overflow detector senses the overflow conditions and a selector responsive to the overflow detector utilizes the modified full-scale range when overflow conditions are sensed.

Abstract: Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode.

Abstract: NOR logic performed by a half current switch emitter follower ("HCSEF") circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ("CSEF") circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.