Abstract: A method for generating a pulse width modulation (PWM) signal, by a processor communicatively coupled to a system memory element, is provided. The method computes, by the processor, a coarse adjustment PWM output signal and a modified fine adjustment input signal, using a low speed clock rate; performs, by the processor, a fine adjustment to the coarse adjustment PWM output signal, using a high speed clock rate, based on the modified fine adjustment input signal; and generates an increased resolution PWM output signal, by the processor, based on the fine adjustment.

Abstract: A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.

Abstract: A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.

Abstract: A method and apparatus are provided to allow at least portions of two fieldbus messages to be stored in a fieldbus device. The fieldbus device includes a media access unit, a fieldbus communication controller, and a controller. The media access unit is coupleable to a fieldbus loop to receive fieldbus signals and provide a digital bitstream related to the fieldbus signals. The fieldbus communication controller assembles data segments relating to at least portions of two fieldbus messages from the bitstream and stores the segments in a receive FIFO memory. The controller is adapted: to read the segments from the receive FIFO memory and act upon fieldbus messages.

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals.