Abstract: Apparatus and a method for implementing prioritized interrupt handling of devices that assert interrupt requests on a shared interrupt request line. The method provides a scheme for handling interrupts in a computing apparatus having a plurality of devices that share a shared interrupt request line, such that interrupt servicing of a device among the plurality of devices that is selected to have a highest priority interrupts servicing of interrupt service routines for the other devices. Each device has a corresponding service routine that has a core service portion including instructions for servicing that device. In response to an assertion of a first interrupt request signal on the shared interrupt request line by one of the devices, the method determines the device that asserted the first interrupt request signal, and initiates execution of a core service portion of the service routine corresponding to the device determined to have asserted the first interrupt.

Abstract: Apparatus and a method for monitoring the time for a computer to process a process associated with an interrupt asserted on a system bus. When the interrupt is asserted, a time stamp value and data associated with the interrupt are stored in one of a plurality of registers. The data associated with the interrupt include an identification of the type of interrupt, the bus, and a device asserting the interrupt. Whenever a time stamp value and associated data are stored in a register, a flag is set ON to indicate information is stored therein. The time stamp value and associated data are stored in an overflow register if every other register is in use. A latency value for the interrupt is determined from the difference between the time stamp value stored in a register and the time when processing of the interrupt process is complete.