Patents by Inventor Paul D. Madland

Paul D. Madland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing circuit for memory employing reset function
    Patent number: 5018111
    Abstract: A timing circuit is described for a single phase clocked memory. The output of a flip-flop is used to initiate the generation of a plurality of control signals through models of circuit elements of the memory such as the word line, bit line, etc. The output of these models are used to generate control signals both when the flip-flop is set and reset. The flip-flop is reset by a signal from one of the models.
    Type: Grant
    Filed: December 27, 1988
    Date of Patent: May 21, 1991
    Assignee: Intel Corporation
    Inventor: Paul D. Madland
  • Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells
    Patent number: 4926387
    Abstract: A timing circuit is described for a single phase clocked memory. A plurality of models duplicating a word line, a bit line, a cell, etc., are used in the timing circuit. The bit line model is scaled down compared to the actual bit line, however, in conjunction with the drive to the bit line (scaled up model of the cell), the signal on the bit line model is greater than the actual signal on the bit line in the array during reading. This simplifies the detection circuitry needed in the timing circuit and provides more accurate control signals.
    Type: Grant
    Filed: December 27, 1988
    Date of Patent: May 15, 1990
    Assignee: Intel Corporation
    Inventor: Paul D. Madland
  • Apparatus for limiting minority carrier injection in CMOS memories
    Patent number: 4727518
    Abstract: A CMOS array is described where the memory cells are formed in n-type wells. No back biasing is employed. To prevent generation of minority carriers within the wells, on-chip filtering of power used for the devices in the wells and for biasing the wells is employed. Other techniques are used to reduce problems associated with minority carrier generation.
    Type: Grant
    Filed: February 17, 1984
    Date of Patent: February 23, 1988
    Assignee: Intel Corporation
    Inventor: Paul D. Madland