Abstract: A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

Abstract: A method for handling memory defects during the POST phase and memory calibration in single processor and multiprocessor information handling systems is disclosed whereby information regarding the location of a known memory defect is utilized to optimize the performance of an information handling system. Memory defects within system memory are identified and replaced during operation with error free memory space.

Abstract: A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

Abstract: A system and method for interrupt processing includes a technique for exiting from interrupt mode in multiple processor systems. Those processors that were in a suspended or halt state immediately before entering the interrupt mode are released immediately with reference to the resolution of the interrupt condition. Those processors not responsible for the processing tasks associated with resolving the interrupt condition serially exit from interrupt mode on a time-delayed basis following the resolution of the interrupt condition.

Abstract: A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

Abstract: A method for synchronizing processors during a system management interrupt caused from a memory hot plug event in multiple processor systems is disclosed. In one embodiment, a method for synchronizing processors during an assertion of a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks necessary for resolving the SMI or a non-interrupt handling processor not assigned to perform the processing tasks necessary for resolving the SMI. The method further includes creating a task structure operable to cause non-interrupt handling processors to perform at least one task for each interrupt handling processor. The method further includes automatically performing the at least one task during the SMI for each non-interrupt handling processor.

Abstract: A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

Abstract: A method for handling memory defects during the POST phase and memory calibration in single processor and multiprocessor information handling systems is disclosed whereby information regarding the location of a known memory defect is utilized to optimize the performance of an information handling system. Memory defects within system memory are identified and replaced during operation with error free memory space.

Abstract: A method for synchronizing processors during a system management interrupt caused from a memory hot plug event in multiple processor systems is disclosed. In one embodiment, a method for synchronizing processors during an assertion of a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks necessary for resolving the SMI or a non-interrupt handling processor not assigned to perform the processing tasks necessary for resolving the SMI. The method further includes creating a task structure operable to cause non-interrupt handling processors to perform at least one task for each interrupt handling processor. The method further includes automatically performing the at least one task during the SMI for each non-interrupt handling processor.

Abstract: A system and method for processing system management interrupts in multiple processor systems is disclosed. In one embodiment, a method for processing a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks necessary for resolving the SMI or a non-interrupt handling processor not assigned to perform the processing tasks necessary for resolving the SMI. The method further including, for each non-interrupt handling processor, setting the non-interrupt handling processor into a wait for Start-up Inter-Processor Interrupt (SIPI) mode. The method further including, for the interrupt handling processor, performing the processing tasks necessary for resolving the SMI such that upon entry into a SMI handler the interrupt handling processor enters and exits the SMI handler without synchronization with the non-interrupt handling processors.

Abstract: Option ROMs associated with information handling system processing components is selectively disabled to reduce the time associated with one or more boots of the information handling system, such as during deployment of applications after manufacture of the information handling system. An Option ROM selector module identifies one or more Option ROMs to disable at a boot, such as Option ROMs associated with processing components that are not needed for deployment of applications, and communicates the disabled Option ROMs to an Option ROM boot execution controller of the information handling system, such as with SMBIOS tokens. At a subsequent boot, the Option ROM execution controller prevents the BIOS from loading disabled Option ROMs for execution so that boot time is reduced with impact to the deployment of applications.