Abstract: The present invention relates to RNAi agents, e.g., double stranded RNA (dsRNA) agents, targeting a solute carrier family member gene, e.g., SLC30A10, or SLC39A8. The invention also relates to methods of using such RNAi agents to inhibit expression of a solute carrier family member gene, e.g., an SLC30A10 gene, or an SLC39A8 gene, and to methods of preventing and treating a solute carrier family member-associated disorder, e.g., a hypermanganesemia.

Abstract: A railroad crossing gate drive mechanism has an adjustable gate arm support in the form of a split hub mounted on the external portion of a drive shaft. A fixed section of the split hub is keyed to the drive shaft and has threaded bolt holes therein. A moveable section of the split hub mounts a gate arm connector and has arcuate slots cut on the same bolt circle as the fixed section's bolt holes. Cap screws extend through the arcuate slots and into the bolt holes. The horizontal position of the gate arm connector can be adjusted due to the loose fit afforded by the arcuate slots on the cap screws. When the gate arm connector is located in the desired horizontal position, the cap screws are tightened to lock the split hub sections together.

Abstract: A railroad crossing gate drive mechanism has an adjustable gate arm support in the form of a split hub mounted on the external portion of a drive shaft. A fixed section of the split hub is keyed to the drive shaft and has threaded bolt holes therein. A moveable section of the split hub mounts a gate arm connector and has arcuate slots cut on the same bolt circle as the fixed section's bolt holes. Cap screws extend through the arcuate slots and into the bolt holes. The horizontal position of the gate arm connector can be adjusted due to the loose fit afforded by the arcuate slots on the cap screws. When the gate arm connector is located in the desired horizontal position, the cap screws are tightened to lock the split hub sections together.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: A method and apparatus for emulating instructions of a microprocessor (“legacy instructions”) with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of “thunk” objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.

Abstract: A method and apparatus for emulating instructions of one microprocessor ("legacy instructions") with instructions of another microprocessor with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, the legacy instructions are translated into direct vectors to software routines for each legacy instruction. Rather than fetching the legacy instruction and interpreting the instruction in software, the emulation system and method in accordance with the present invention fetches the direct vectors to the software routines which emulate the legacy instructions. The legacy instructions can either be translated by way of software when the legacy memory is loaded or modified, or by way of hardware when legacy memory is accessed. By fetching the direct vectors, the need for software-based look-up tables for interpreting the legacy instructions is obviated.