Patents by Inventor Paul Damien McCann

Paul Damien McCann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7153757
    Abstract: A semiconductor substrate (1) comprises first and second silicon wafers (2,3) directly bonded together with interfacial oxide and interfacial stresses minimised along a bond interface (5), which is defined by bond faces (7) of the first and second wafers (2,3). Interfacial oxide is minimised by selecting the first and second wafers (2,3) to be of relatively low oxygen content, well below the limit of solid solubility of oxygen in the wafers. In order to minimise interfacial stresses, the first and second wafers are selected to have respective different crystal plane orientations. The bond faces (7) of the first and second wafers (2,3) are polished and cleaned, and are subsequently dried in a nitrogen atmosphere. Immediately upon being dried, the bond faces (7) of the first and second wafers (2,3) are abutted together and the wafers (2,3) are subjected to a preliminary anneal at a temperature of at least 400° C. for a time period of a few hours.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: December 26, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Paul Damien McCann, William Andrew Nevin
  • Patent number: 6955988
    Abstract: A semiconductor substrate (1) comprising an SOI (2) formed therein. The semiconductor substrate (1) comprises first and second wafers (4,6) which are directly bonded together along a bond interface (9). Prior to bonding the wafers (4,6), a portion (15) of the second wafer (6) is ion implanted to form a p+ region for facilitating selective etching thereof to form a buried cavity (16), in which a buried insulating layer is subsequently formed under a portion (10) of the first wafer (4) for forming the SOI (2). After bonding of the first and second wafers (4,6) a communicating opening (20) is etched through the first wafer (4) to the bond interface (9), and the selectively etchable portion (15) is etched through the communicating opening (20) to form the buried cavity (16). The buried cavity (16) is then filled with deposited oxide to form the buried insulating layer (11).
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: October 18, 2005
    Assignee: Analog Devices, Inc.
    Inventors: William Andrew Nevin, Paul Damien McCann
  • Publication number: 20040087109
    Abstract: A semiconductor substrate (1) comprises first and second silicon wafers (2,3) directly bonded together with interfacial oxide and interfacial stresses minimised along a bond interface (5), which is defined by bond faces (7) of the first and second wafers (2,3). Interfacial oxide is minimised by selecting the first and second wafers (2,3) to be of relatively low oxygen content, well below the limit of solid solubility of oxygen in the wafers. In order to minimise interfacial stresses, the first and second wafers are selected to have respective different crystal plane orientations. The bond faces (7) of the first and second wafers (2,3) are polished and cleaned, and are subsequently dried in a nitrogen atmosphere. Immediately upon being dried, the bond faces (7) of the first and second wafers (2,3) are abutted together and the wafers (2,3) are subjected to a preliminary anneal at a temperature of at least 400° C. for a time period of a few hours.
    Type: Application
    Filed: August 29, 2003
    Publication date: May 6, 2004
    Inventors: Paul Damien McCann, William Andrew Nevin
  • Publication number: 20030148592
    Abstract: A method for bonding a pair of silicon wafers (2,3) together to form a semiconductor wafer (1) wherein an interface surface (5) of one of the silicon wafers (3) is pretreated by an ion implantation or diffusion process prior to bonding of the silicon wafers (2,3). The method includes subjecting the pretreated interface surface (5) to an initial anneal step at approximately 700° C. for 60 minutes for recrystallising the interface surface, and then subjecting both interface surfaces (4,5) to two cleaning steps with respective first and second cleaning solutions, neither of which contain sulphuric acid. The first cleaning solution comprises hydrogen peroxide, ammonia and water, while the second cleaning solution comprises hydrofluoric acid and water. The respective interface surfaces (4,5) are rinsed with water after each cleaning step, and the silicon wafers (2,3) are bonded by anneal bonding at a temperature of the order of 1,150° C. for approximately 60 minutes.
    Type: Application
    Filed: October 29, 2002
    Publication date: August 7, 2003
    Inventors: William Andrew Nevin, Paul Damien McCann, Garry Patrick O'Neill