Abstract: The improved reed relay package provided a “pseudo” Form C relay that includes two Form A relays with at least one bridge filter element electrically interconnecting the signal outputs thereof to reduce stub capacitance and improve RF performance. As a result, the reed relay package can operate at very high frequencies, such as 18 GHz and higher. Also, vias can be provided through the support substrate to simulate a co-planar waveguide and RF shields profiled with cut-outs to better simulate a 50 ohm impedance environment throughout the path of the signal line.

Abstract: An interface structure for use in a semiconductor integrated circuit tester for connecting a test head interface to a DUT interface includes a first frame member having first and second opposite main faces, a second frame member having first and second opposite main faces, and a spacer securing the first and second frame members together in spaced relationship. A first cable assembly header is received in an aperture of the first frame member and includes a conductive element and electrically conductive terminal members exposed at a main face of the first frame member and electrically insulated from the conductive element of the first header. A second cable assembly header is received in an aperture of the second frame member and includes a conductive element and electrically conductive terminal members exposed at a main face of the second frame member and electrically insulated from the conductive element of the second header.

Abstract: A relay controller intermittently connects a power supply across a relay coil with a controlled duty cycle whenever the relay coil is to generate a magnetic field for opening or closing the relay's contacts. The duty cycle with which the controller connects the power supply across the coil controls limits a steady-state amplitude of current passing through the coil, thereby controlling the intensity of the magnetic field the coil generates.

Abstract: Variation in temperature of a digital logic circuit that temporarily increases its heat production after a digital input signal changes state is limited using a heater that applies heat to the digital logic circuit at a variable rate. A control circuit monitors all of the circuit's digital input signals and temporarily decreases the rate at which the heater applies heat to the digital logic circuit after each state change in a digital input signal. The amount of temporary reduction in heater output is sized to substantially match the amount of temporary increase in logic circuit heat production so that the temperature of the logic circuit remains largely unaffected. A feedback circuit is also provided to monitor the temperature of the digital logic circuit and to further adjust the heater output so as to help maintain the logic circuit at a desired temperature.

Abstract: An arbitrary waveform generator (AWG) for producing an analog output current signal includes a random access memory (RAM), a programmable logic device (PLD), a programmable pattern generator, several digital-to analog converters (DACS) and a current multiplexer. The RAM store data sequences representing the analog waveform to be generated. The pattern generator read addresses the RAM causing it to sequentially read out its stored data sequence to the PLD. The PLD routes selected fields of each data sequence word to one or more of the DACs in response to timing signals provided by the pattern generator. Each DAC produces an output current of magnitude determined by its input waveform and range data. The pattern generator also signals the analog multiplexer to sum currents produced by one or more selected DACs to produce the AWG output waveform.

Abstract: An arbitrary waveform generator (AWG) generates an output signal that linearly ramps between discrete levels to approximate a smoothly varying waveform. The AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's output signal.

Abstract: A relay includes contacts residing within a glass tube. A coil surrounding the tube and a switch are connected in parallel between two terminals of the relay. A current source supplies a current to the coil and switch. When the switch is open, substantially all of the current passes through the coil and the coil produces a sufficient amount of magnetic flux to close the relay's contacts. When the switch closes, it shunts a sufficient amount of the current away from the coil to reduce the magnetic flux it produces below the level needed to keep the contacts closed. The current source is sized so that the coil requires relatively few turns, thereby allowing the relay to be relatively thin. The coil is formed by a conductor embedded in an insulating substrate surrounding the tube.

Abstract: An integrated circuit (IC) tester includes a separate arbitrary waveform generator (AWG) for each input terminal of an IC to be tested. Each AWG generates a test signal input to the IC terminal that linearly ramps between discrete levels to approximate a smoothly varying waveform. Each AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's test signal.

Abstract: An integrated circuit (IC) tester includes a separate arbitrary waveform generator (AWG) for each input terminal of an IC to be tested. Each AWG generates a test signal input to the IC terminal that linearly ramps between discrete levels to approximate a smoothly varying waveform. Each AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's test signal.

Abstract: A drive circuit for an integrated circuit tester operates in either a drive mode of a termination mode. In the drive mode, the drive circuit supplies a differential test signal to an integrated circuit device under test (DUT) via a pair of transmission lines. In its termination mode, the drive circuit terminates the transmission lines with their characteristic impedances and provides an adjustable load to a DUT output signal appearing on the transmission lines.

Abstract: A drive circuit for an integrated circuit tester operates in either a drive mode of a termination mode. In the drive mode, the drive circuit supplies a differential test signal to an integrated circuit device under test (DUT) via a pair of transmission lines. In its termination mode, the drive circuit terminates the transmission lines with their characteristic impedances and provides an adjustable load to a DUT output signal appearing on the transmission lines.