Patents by Inventor Paul Darren Hoxey
Paul Darren Hoxey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10861575Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.Type: GrantFiled: October 28, 2019Date of Patent: December 8, 2020Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
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Publication number: 20200066365Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.Type: ApplicationFiled: October 28, 2019Publication date: February 27, 2020Inventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
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Patent number: 10460822Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.Type: GrantFiled: August 23, 2017Date of Patent: October 29, 2019Assignee: ARM LimitedInventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
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Publication number: 20190066814Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.Type: ApplicationFiled: August 23, 2017Publication date: February 28, 2019Inventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
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Publication number: 20160118091Abstract: The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.Type: ApplicationFiled: October 23, 2014Publication date: April 28, 2016Inventors: Plamen Asenov ASENOV, David Anthony NEW, Paul Darren HOXEY
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Patent number: 9324392Abstract: The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.Type: GrantFiled: October 23, 2014Date of Patent: April 26, 2016Assignee: ARM LimitedInventors: Plamen Asenov Asenov, David Anthony New, Paul Darren Hoxey
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Patent number: 8067971Abstract: A latch circuit for retaining and transmitting an input data value is disclosed, along with a memory, and a method for retaining and transmitting data. The latch circuit includes a primary input for receiving a data value, an output for outputting the data value, a data transmission path including a transmitting device for transmitting the data value from the primary input to the output, a feedback loop for retaining the data value, the feedback loop including the transmitting device and a further device. The further device is configured to turn on in response to assertion of an activating signal and to turn off in response to no assertion of the activating signal.Type: GrantFiled: September 18, 2009Date of Patent: November 29, 2011Assignee: ARM LimitedInventor: Paul Darren Hoxey
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Patent number: 8045401Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronized with each other.Type: GrantFiled: September 18, 2009Date of Patent: October 25, 2011Assignee: ARM LimitedInventors: Yew Keong Chong, Gus Yeung, Paul Darren Hoxey, Paul Stanley Hughes, Gary Robert Waggoner
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Publication number: 20110068842Abstract: A latch circuit for retaining and transmitting an input data value is disclosed, along with a memory, and a method for retaining and transmitting data.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: ARM LIMITEDInventor: Paul Darren Hoxey
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Publication number: 20110072323Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: ARM LimitedInventors: Yew Keong Chong, Gus Yeung, Paul Darren Hoxey, Paul Stanley Hughes, Gary Robert Waggoner
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Patent number: 7876634Abstract: A data processing system comprising a memory array having a plurality of memory cells and read circuitry for reading a logic value stored in one of the plurality of memory cells. The read circuitry is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.Type: GrantFiled: December 2, 2005Date of Patent: January 25, 2011Assignee: ARM LimitedInventors: David New, Paul Darren Hoxey, David Michael Bull, Shidhartha Das
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Patent number: 7855924Abstract: A memory circuit includes a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit includes a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is configured to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.Type: GrantFiled: May 19, 2006Date of Patent: December 21, 2010Assignee: ARM LimitedInventors: David New, Paul Darren Hoxey, David Michael Bull, Shidhartha Das
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Patent number: 7558104Abstract: An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.Type: GrantFiled: February 5, 2007Date of Patent: July 7, 2009Assignee: ARM LimitedInventors: Andrew John Sowden, David Anthony New, Paul Darren Hoxey, Simon Christopher Reynolds
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Publication number: 20090161442Abstract: A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.Type: ApplicationFiled: December 2, 2005Publication date: June 25, 2009Applicant: ARM LIMITEDInventors: David New, Paul Darren Hoxey, David Michael Bull, Shidhartha Das
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Publication number: 20080189483Abstract: An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.Type: ApplicationFiled: February 5, 2007Publication date: August 7, 2008Applicant: ARM LimitedInventors: Andrew John Sowden, David Anthony New, Paul Darren Hoxey, Simon Christopher Reynolds
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Publication number: 20070268755Abstract: A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit comprises a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is provided to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.Type: ApplicationFiled: May 19, 2006Publication date: November 22, 2007Applicant: ARM LimitedInventors: David New, Paul Darren Hoxey, David Michael Bull, Shidhartha Das
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Patent number: 6785179Abstract: A memory circuit 2 includes a plurality of memory cells 4, 6 which are subject to memory access operations. These memory access operations serve to selectively discharge one or more of the bit lines A, Abar, B, Bbar associated with the memory cells 4, 6. During a subsequent precharge operation serving to restore the precharged voltage levels of the bit lines A, Abar, B Bbar charge sharing is performed between non-accessed bit lines and those which have been accessed and accordingly at least partially discharged. Also the precharging circuits 12, 14, 16, 18 associated with the non-accessed bit lines contribute towards the precharging operation.Type: GrantFiled: June 19, 2003Date of Patent: August 31, 2004Assignee: Arm LimitedInventors: David Michael Bull, Paul Darren Hoxey