Patents by Inventor Paul David Agnello
Paul David Agnello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7993990Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: GrantFiled: April 9, 2010Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devendra K. Sadana
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Publication number: 20100197118Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devendra K. Sadana
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Patent number: 7696573Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: GrantFiled: October 31, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devandra K. Sadana
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Publication number: 20090108302Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devandra K. Sadana
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Patent number: 7081676Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: October 22, 2003Date of Patent: July 25, 2006Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
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Patent number: 6809030Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: June 28, 2002Date of Patent: October 26, 2004Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
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Publication number: 20040087160Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: ApplicationFiled: October 22, 2003Publication date: May 6, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul David Agnello, Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
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Publication number: 20020182836Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2layer in said structure.Type: ApplicationFiled: June 28, 2002Publication date: December 5, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul David Agnello, Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
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Patent number: 6440851Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: October 12, 1999Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
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Patent number: 5897349Abstract: A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain junction, and is preferably of greater width than the gate.Type: GrantFiled: May 23, 1996Date of Patent: April 27, 1999Assignee: International Business Machines CorporationInventor: Paul David Agnello
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Patent number: 5796166Abstract: A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.Type: GrantFiled: June 21, 1996Date of Patent: August 18, 1998Assignee: IBM CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Alfred Grill, Christopher Vincent Jahnes, Thomas John Licata, Ronnen Andrew Roy
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Patent number: 5776823Abstract: A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.Type: GrantFiled: May 8, 1996Date of Patent: July 7, 1998Assignee: IBM CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Alfred Grill, Christopher Vincent Jahnes, Thomas John Licata, Ronnen Andrew Roy
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Patent number: 5654570Abstract: A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain junction, and is preferably of greater width than the gate.Type: GrantFiled: April 19, 1995Date of Patent: August 5, 1997Assignee: International Business Machines CorporationInventor: Paul David Agnello