Patents by Inventor Paul David Ranucci

Paul David Ranucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive capacitor charge/discharge network
    Patent number: 7839203
    Abstract: An adaptive capacitor charge/discharge network tailors the rate-of-change of a capacitor. The network includes two circuit groups with two or more parallel circuit branches, each branch including a current source and a controllable switch connected in series. The parallel circuit branches of one group are connected to Vss, and the parallel circuit branches of the other group are connected to Vdd. All the parallel circuit branches are connected to one plate of a capacitor, the other plate of the capacitor is connected to either Vss or Vdd. A control circuit controls the switch status, and incrementally controls the charge/discharge of the capacitor according to a predetermined order and a predetermined timing sequence to achieve a desired tailored charge/discharge curve.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: November 23, 2010
    Assignee: National Semiconductor Corporation
    Inventors: William MacLean, Paul David Ranucci
  • Metal oxide semiconductor (MOS) bandgap voltage reference circuit
    Patent number: 6933770
    Abstract: A metal oxide semiconductor (MOS) bandgap voltage reference circuit with a plurality of dummy bipolar junction transistors (BJTs) coupled to the mismatched parasitic substrate BJTs for improving parasitic capacitance matching, thereby improving startup behavior of the bandgap reference circuitry.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: August 23, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Paul David Ranucci
  • Metal oxide semiconductor (MOS) bandgap voltage reference circuit
    Patent number: 6858917
    Abstract: A metal oxide semiconductor (MOS) bandgap voltage reference circuit with a plurality of dummy bipolar junction transistors (BJTs) coupled to the mismatched parasitic substrate BJTs for improving parasitic capacitance matching, thereby improving startup behavior of the bandgap reference circuitry.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: February 22, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Paul David Ranucci