Patents by Inventor Paul de Dood
Paul de Dood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10796053Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: GrantFiled: September 24, 2018Date of Patent: October 6, 2020Assignee: Arm LimitedInventors: Paul de Dood, Marlin Wayne Frederick, Jr., Jerry Chaoyuan Wang, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Daniel J. Albers, David William Granda
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Publication number: 20190026417Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Paul de Dood, Marlin Wayne Frederick, JR., Jerry Chaoyuan Wang, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Daniel J. Albers, David William Granda
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Patent number: 10083269Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: GrantFiled: October 30, 2014Date of Patent: September 25, 2018Assignee: ARM LimitedInventors: Paul De Dood, Marlin Wayne Frederick, Jerry Chaoyuan Wang, Brian Douglas Ngai Lee, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Yanbin Jiang, Emmanuel Jean Marie Olivier Pacaud, Matthieu Domonique Henri Pauly, Sylvia Xiuhui Li, Thanusree Achuthan, Daniel J. Albers, David William Granda
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Publication number: 20180225402Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: ApplicationFiled: October 30, 2014Publication date: August 9, 2018Inventors: Paul DE DOOD, Marlin Wayne Frederick, JR., Jerry Chaoyuan Wang, Brian Douglas Ngai Lee, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Yanbin Jiang, Emmanuel Jean Marie Olivier Pacaud, Matthieu Domonique Henri Pauly, Sylvia Xiuhui Li, Thanusree Achuthan, Daniel J. Albers, David William Granda
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Patent number: 9659125Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.Type: GrantFiled: January 28, 2014Date of Patent: May 23, 2017Assignee: ARM LimitedInventor: Paul de Dood
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Publication number: 20150213177Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.Type: ApplicationFiled: January 28, 2014Publication date: July 30, 2015Applicant: ARM LIMITEDInventor: Paul DE DOOD
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Publication number: 20150143309Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: ApplicationFiled: October 30, 2014Publication date: May 21, 2015Inventors: Paul DE DOOD, Marlin Wayne Frederick, Jerry Chaoyuan Wang, Brian Douglas Ngai Lee
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Patent number: 7594202Abstract: The present invention comprises a method of optimizing a circuit design having a plurality of library cells. In one embodiment, the method includes the steps of providing a plurality of logically equivalent cells that vary in at least one design parameter, the plurality of logically equivalent cells having a relatively continuous spectrum of values of one of the design parameters, evaluating a selected characteristic of the circuit design; and replacing a cell in the circuit design with a cell an equivalent cell.Type: GrantFiled: July 20, 2006Date of Patent: September 22, 2009Assignee: Prolific, Inc.Inventors: Paul de Dood, Brian Lee, Daniel Albers
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Patent number: 7594203Abstract: The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are in the same fan-in and fan-out cones. This property allows full timing analysis to be performed on a design such that multiple alternatives are explored in parallel and accurate results are obtained. By ordering the choice of cell instances to change and by ordering the alternatives to try, a greater degree of optimization is found earlier in the process.Type: GrantFiled: January 24, 2007Date of Patent: September 22, 2009Assignee: Prolific, Inc.Inventors: Paul de Dood, Brian Lee, Daniel Albers
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Publication number: 20080178128Abstract: The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are in the same fan-in and fan-out cones. This property allows full timing analysis to be performed on a design such that multiple alternatives are explored in parallel and accurate results are obtained. By ordering the choice of cell instances to change and by ordering the alternatives to try, a greater degree of optimization is found earlier in the process.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Inventors: Paul de Dood, Brian Lee, Daniel Albers
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Patent number: 7107551Abstract: A method and apparatus for optimizing a circuit design using a library of cells in which a continuous spectrum of cells are provided. A library containing real and virtual cells is used so that cells can be selected across a wide spectrum of a design parameter, such as drive strength. The cells are provided in discrete steps small enough that the effect of having a continuous spectrum of cells is achieved. After optimization, only the cells finally selected need be actually synthesized, and when these constitute a small percentage of the total number of cells, the impact to library size and final placement and routing is minimized. Thus the ability to optimize across a continuous spectrum is achieved while preserving a cell library based design flow.Type: GrantFiled: May 30, 2003Date of Patent: September 12, 2006Assignee: Prolific, Inc.Inventors: Paul de Dood, Brian Lee, Daniel Albers