Abstract: Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. A resource access controller controls access to resources addressed by at least one central processing unit. The resource access controller includes an address translation mechanism providing fake response identification as to whether or not a response is to be faked. The resource access controller also includes a fake response generator for selectively generating a faked response where the fake response identification of the corresponding translation entry indicates that a response is to be faked. The resource access controller is able to associate fake response indications with a resource and to generate a fake response when an attempt is made to access a resource labeled such that a faked response should be returned.

Abstract: To provide efficient resource access control in a computer system, a trap handler for handling a trap in the event of a faulty resource access being detected is arranged to define a diversion for subsequent access attempts to the same resource. An address translation mechanism is responsive to indication of a diversion for a resource access to modify an address mapping, whereby subsequent attempts to access the resource are diverted in accordance with the diversion. The trap handler can be arranged in a conventional manner to process an exception of the first faulty access to the resource. However, by defining the diversion, which can be used to map further attempts to access the same resource, unnecessary exception processing can be avoided.

Abstract: A method of controlling a computer system running one or more application programs and an operating system incorporating a kernel involves providing a privileged mode for executing routines associated with said kernel, and a non-privileged mode for executing routines associated with an application program, locating the kernel within a first region of memory, and the application program in a second region of memory, and setting the system to privileged mode in response to accessing code in said first region of memory and to non-privileged mode in response to accessing code in said second region of memory.

Abstract: A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

Abstract: A computer system is provided including a processor, a memory (such as RAM) having a plurality of locations for storing data, and a controller. A data communications facility (such as a bus) interconnects the processor and the controller, while the controller is in turn coupled to the memory. The controller is responsive to a single command received from the processor to copy data from a first memory location to a second memory location, as specified within the command. By copying data in this manner, processor and bus bandwidth can be preserved.

Abstract: In a computer processing apparatus, when writing data to, and/or reading data from, memory, one or more instruction bits are associated with the memory address for the data to specify how encryption or decryption is to be performed. The bit(s) may be part of the memory address or separate therefrom, for example as a data header. Multiple data paths provided to write data to, and read data from, memory. On at least one of the paths is hardware operable to perform encryption or decryption. Preferably at least one path is a non-encryption/decryption path. The path to be used to write the data to, or read the data from, memory is chosen in accordance with the instruction bits associated with the memory address.

Abstract: A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

Abstract: A computer system comprises a processor (2), memory (4) and a plurality of devices (6, 8, 10, 12), the processor (2) and the memory (4) being operable to effect the operation of a fault response processor (AFR), and a device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices. The fault response processor (AFR) is operable to generate a model (81) which represents the processor (2), the memory (4) and the devices (6, 8, 10, 12) of the computer system and the inter-connection of the processor (2), memory (4) and the devices (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL). The device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices (6, 8, 10, 12) is arranged, consequent upon a change of operational status of the device, to generate fault report data indicating whether the change of status was caused internally within the device or externally by another connected device. The devices of the computer system may be formed as a plurality of Field Replaceable Units (FRU).

Abstract: A device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for use in a computer system comprising a processor (P), memory (M) and a device (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) operatively coupled to the computer system the device driver being operable to control the device to monitor an operational status of the device, and consequent upon a change in the operational status to generate a fault report data indicating whether the change of status was caused internally within the device or externally by another connected device which caused the change of operational status to occur. The fault reports may also include an indication of the operational status of the device. Furthermore, if the fault report data indicates that the change of status was caused externally, the device driver may generate fault direction information indicative of an apparent direction on a connection between the device and the other device suspected as causing the indicated external fault.

Abstract: A live snapshot of a first storage that is logically subdivided into a plurality of blocks is generated in a running computer system a manner to minimise the impact on the running of the computer system. On initiating the snapshot, the content of a portion of the first storage that includes at least one block is copying to snapshot storage and a copied indication for each copied block is recording in a copy map. In response to any write request to a block for which no copied indication has been recorded in the copy map, the content of the block is copied to the snapshot storage, prior to writing to that block. A copied indication for the copied block is also recorded in the copy map. The content of other blocks for which no copied indication has been recorded in the copy map is successively copied to the snapshot storage. A copied indication for each copied block is also recorded in the copy map.

Abstract: A memory controller controls access to one or more memory units. The memory controller includes access control logic operable to receive a memory access request that references at least one memory address. It further includes a fake response record operable to record a fake response indication for an address for which a response is to be faked. The access control logic is operable on receipt of a memory access request to access the fake response record and to fake a response where a fake response indication for an address indicates that a response is to be faked. By providing such a faked response, an embodiment of the invention is able avoid multiple exceptions for the same memory location in a CPU. Also, by providing such a faked response, multiple bus errors for a memory location can also be avoided where a bus supports Direct Memory Access (DMA). The memory controller can be implemented in an integrated circuit.

Abstract: Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. The resource can be a memory location, a peripheral or any other addressable system component. A resource access mechanism in a processor controls access to resources. The resource access mechanism includes an address control mechanism having a plurality of address control entries, each address control entry providing fake response identification indicating whether or not a response for the corresponding address is to be faked. The resource access mechanism also includes a fake response generator for selectively generating a faked response for an address in response to the fake response identification of the corresponding address control entry indicating that a response is to be faked.

Abstract: To provide efficient resource access control in a computer system, a trap handler for handling a trap in the event of a faulty resource access being detected is arranged to define a diversion for subsequent access attempts to the same resource. An address translation mechanism is responsive to indication of a diversion for a resource access to modify an address mapping, whereby subsequent attempts to access the resource are diverted in accordance with the diversion. The trap handler can be arranged in a conventional manner to process an exception of the first faulty access to the resource. However, by defining the diversion, which can be used to map further attempts to access the same resource, unnecessary exception processing can be avoided.

Abstract: Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. A resource access controller controls access to resources addressed by at least one central processing unit. The resource access controller includes an address translation mechanism providing fake response identification as to whether or not a response is to be faked. The resource access controller also includes a fake response generator for selectively generating a faked response where the fake response identification of the corresponding translation entry indicates that a response is to be faked. The resource access controller is able to associate fake response indications with a resource and to generate a fake response when an attempt is made to access a resource labeled such that a faked response should be returned.