Abstract: Surface mount device (SMD) placement to control a signal path in a printed circuit board (PCB), including: adding, to a PCB, a plurality of signal path segments, each signal path segment of the plurality of signal path segments ending at corresponding pad of a plurality of pads, wherein a first pad of the plurality of pads is couplable to a second pad of the plurality of pads to create a first signal path and is couplable to a third pad of the plurality of pads to create a second signal path; and coupling, via a discrete SMD, the first pad and the second pad to create the first signal path comprising a first signal path segment of the plurality of signal path segments and a second signal path segment of the plurality of signal path segments.

Abstract: Surface mount device (SMD) placement to control a signal path in a printed circuit board (PCB), including: adding, to a PCB, a plurality of signal path segments, each signal path segment of the plurality of signal path segments ending at corresponding pad of a plurality of pads, wherein a first pad of the plurality of pads is couplable to a second pad of the plurality of pads to create a first signal path and is couplable to a third pad of the plurality of pads to create a second signal path; and coupling, via a discrete SMD, the first pad and the second pad to create the first signal path comprising a first signal path segment of the plurality of signal path segments and a second signal path segment of the plurality of signal path segments.

Abstract: Method, apparatus and computer program product for spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency response comprising acquiring a sample waveform including a set of discrete uniformly spaced samples from a target system, wherein the sample waveform is a time domain vector; applying FFT transforming the time domain vector into the frequency domain; analyzing the frequency domain response including calculating the magnitude response; and determining whether the sample waveform has spurs including comparing the magnitude response to an average noise floor threshold including determining that the magnitude response having an average noise floor value above the average noise floor threshold has one or more spurs and determining that the magnitude response having an average noise floor value below the average noise floor threshold has no spurs, wherein a spur indicates unaligned data having a delayed bit flip.

Abstract: Method, apparatus and computer program product for spur detection in a sampled waveform in a mixed analog/digital system using the phase of the frequency response comprising acquiring a sample waveform including a set of discrete uniformly spaced samples from a target system, wherein the sample waveform is a time domain vector; applying FFT transforming the time domain vector into the frequency domain; analyzing the frequency domain response including calculating the phase response; and determining whether the sample waveform has spurs including comparing the phase response to a clean phase profile including determining that the phase response having a phase profile value outside a phase deviation tolerance has one or more spurs and determining that the phase response having a phase profile value inside the phase deviation tolerance has no spurs, wherein a spur indicates unaligned data having a delayed bit flip.

Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract: Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process.

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract: An apparatus and method detect microchip tampering by including a capacitance circuit that comprises a protective cover. Dielectric material may be sandwiched between the cover and a backside metal layer, which may be proximate a protected surface of the microchip. Changes in the capacitance of the above circuit caused by alteration of the cover or other component of the capacitance circuit may be sensed and prompt defensive action.

Abstract: Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically include metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract: System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. The placement manager inserts specifications for at least one de-gassing opening in the physical design for the electronic package, wherein the specification for at least one de-gassing opening are created in accordance with said design constraints regarding said physical design of said electronic package. The placement manager outputs an updated physical design of the electronic package.

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract: Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically comprise metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Abstract: A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the first coating, in electrical communication with the ground pads. The first coating is sufficiently thick to achieve a consistent characteristic impedance when the second coating is applied.

Abstract: Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process.

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.