Abstract: A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2.sup.P possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range.

Abstract: A sub-band coder for video signals is disclosed, which is easily realizable in VLSI due to its simple structure. The coder uses sets of two-tap finite impulse response (FIR) filters having equal-magnitude coefficients to decompose the video signal at multiple stages. In the preferred embodiment the sub-band coder has an asymmetrical structure. With the arrangement, the sub-band decomposition effects what is equivalent to a multiple block-size Hadamard transform of the video signal in which coefficients are transmitted from various block-sized transforms of larger blocks of pixel data.

Abstract: A switched capacitor oscillator is constructed by providing a damped resonator network with a comparator as a nonlinear feedback element by connecting the input of the comparator to the output of a first operational amplifier of the resonator network and connecting the output of the comparator to the input of the resonator network. The comparator thus becomes a saturable positive feedback element for the resonator network. Also disclosed is a startup network for the oscillator and an input network which derives an input from a reference voltage in order to eliminate supply voltage noise and provide precision control of amplitude.

Abstract: A capacitor-resistor-capacitor (CRC) element for active filter realization, which is fully integrable and compatible with MOS technology, is described. The incorporation of the CRC element in a semiconductor integrated circuit active filter also is described. The structure of the CRC filter element is closely analogous to a depletion mode MOS field effect device, except that the channel zone 26 is doped to a level which substantially precludes conductivity modulation at the usual operating voltages. However, the doping level is such as to enable the use of the channel zone as a semiconductor resistance element. Thus, the N-channel CRC element realized in the NMOS technology comprises a first capacitance composed of the gate 27, gate dielectric 38, and resistive channel 26, paralleled by the resistive channel 26 itself constituting a resistor, and then the underlying PN junction capacitance between the N-type resistive channel 26 and the underlying P-type semiconductor body portion 21.

Abstract: Because of the very large variety of useful filter configurations, it is highly desirable to have a generalized circuit topology from which all specific filters can be derived. A generalized switched-capacitor biquadratic active filter comprises a pair of operational amplifiers (10, 11), each of which has an unswitched feedback capacitor (D, B) connected between its output port (3, 3') and its inverting input port (1, 1'). A third through-switched capacitor (C) provides feedback between the output port (3') of the second amplifier (11) and the inverting input port (1) of the first amplifier (10). A diagonally-switched capacitor (A) couples the output port (3) of the first amplifier (10) to the inverting input port (1') of the second amplifier (11). The noninverting input ports (2, 2') of the two amplifiers are connected to signal ground.

Abstract: Switched capacitor topologies currently in use are susceptible to the deleterious effects of the parasitic capacitances associated with the switches. Topologies that are immune to these effects are disclosed. A first such embodiment comprises a first switch (22, 32), a capacitor (23, 33), and a second switch (24, 34) connected in series between one input terminal (1) and one output terminal (3) of the network. Third and fourth switches (26, 35 and 27, 36) are connected between the junctions (98, 42 and 99, 43) of the capacitor and the first and second switches, respectively, and the common junction (97, 41) of the second input and second output terminals (2, 4). A second embodiment is also disclosed.

Abstract: A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2.sub.P possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range.