Patents by Inventor Paul E. Gregory
Paul E. Gregory has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10989748Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.Type: GrantFiled: July 17, 2020Date of Patent: April 27, 2021Assignee: Micron Technology, Inc.Inventors: Paul E. Gregory, Randon K. Richards
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Publication number: 20200348349Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Inventors: Paul E. Gregory, Randon K. Richards
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Patent number: 10718805Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.Type: GrantFiled: May 26, 2017Date of Patent: July 21, 2020Assignee: Micron Technology, Inc.Inventors: Paul E. Gregory, Randon K. Richards
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Patent number: 10325986Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: GrantFiled: October 20, 2016Date of Patent: June 18, 2019Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Patent number: 10217838Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: April 26, 2018Date of Patent: February 26, 2019Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20180261683Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: April 26, 2018Publication date: September 13, 2018Applicant: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 10014387Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: February 18, 2016Date of Patent: July 3, 2018Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20170356946Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.Type: ApplicationFiled: May 26, 2017Publication date: December 14, 2017Inventors: Paul E. Gregory, Randon K. Richards
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Patent number: 9812550Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: January 30, 2017Date of Patent: November 7, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20170141209Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20170040419Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Patent number: 9508800Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: GrantFiled: December 22, 2015Date of Patent: November 29, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Publication number: 20160181370Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: ApplicationFiled: December 22, 2015Publication date: June 23, 2016Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Publication number: 20160163823Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9299698Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: June 25, 2013Date of Patent: March 29, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9263523Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.Type: GrantFiled: February 24, 2014Date of Patent: February 16, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
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Patent number: 9111785Abstract: A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.Type: GrantFiled: July 31, 2013Date of Patent: August 18, 2015Assignee: Mie Fujitsu Semiconductor LimitedInventors: Paul E. Gregory, Pushkar Ranade, Lucian Shifren
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Patent number: 9093469Abstract: An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.Type: GrantFiled: May 9, 2014Date of Patent: July 28, 2015Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lucian Shifren, Scott E. Thompson, Paul E. Gregory
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Patent number: 9041126Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.Type: GrantFiled: September 5, 2013Date of Patent: May 26, 2015Assignee: Mie Fujitsu Semiconductor LimitedInventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim
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Publication number: 20140248753Abstract: An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants.Type: ApplicationFiled: May 9, 2014Publication date: September 4, 2014Applicant: SuVolta, Inc.Inventors: Lucian Shifren, Scott E. Thompson, Paul E. Gregory