Abstract: The output frequency of a phase locked loop frequency synthesizer is measured by a counter which counts whole output cycles and a timer providing a signal proportional to a fractional output cycle during a sampling period. The counter output is stored into a latch at each sampling period. Calculated frequency is generated by an accumulator which is incremented a selectable integer N at the completion of each sampling period. The accumulator output is divided into a first part relating to whole cycles and a second part relating to fractional cycles. An adder takes the difference of the latch stored number and the accumulator output first part. The resulting difference, with the accumulator output second part restored thereto, comprises a coarse error signal in digital form. The digital coarse error signal is converted to analog and applied as one input to a summer. A second input to the summer is provided by the timer signal after being scaled proportionately to N in a multiplying D/A converter.