Abstract: Exemplary methods are provided for storing data in a flash storage device to facilitate subsequent detection of tampering, comprising receiving a plaintext; reading first metadata associated with a device sector; encrypting the plaintext based on the first metadata to generate a cipher text and first authentication data; storing the cipher text in the sector; and storing the first authentication data as second metadata associated with the sector. Exemplary methods are also provided for detecting tampering with data stored in a flash storage device, comprising determining a physical location in a device sector; reading cipher text from the physical location; reading first authentication data and maintenance metadata associated with the sector; decrypting the cipher text based on a user key and the maintenance metadata to generate second authentication data; and determining the occurrence of tampering based on the first and second authentication data. Memory devices embodying said methods are also provided.

Abstract: Exemplary methods are provided for storing data in a flash storage device to facilitate subsequent detection of tampering, comprising receiving a plaintext; reading first metadata associated with a device sector; encrypting the plaintext based on the first metadata to generate a cipher text and first authentication data; storing the cipher text in the sector; and storing the first authentication data as second metadata associated with the sector. Exemplary methods are also provided for detecting tampering with data stored in a flash storage device, comprising determining a physical location in a device sector; reading cipher text from the physical location; reading first authentication data and maintenance metadata associated with the sector; decrypting the cipher text based on a user key and the maintenance metadata to generate second authentication data; and determining the occurrence of tampering based on the first and second authentication data. Memory devices embodying said methods are also provided.

Abstract: A method comprises receiving a plaintext message (m), encrypting the plaintext message and generating a cipher text (c) and authentication data (t), storing the cipher text in a user data portion of a data storage device, and storing the authentication data in a meta data portion of the data storage device.

Abstract: A method comprises receiving a plaintext message (m), encrypting the plaintext message and generating a cipher text (c) and authentication data (t), storing the cipher text in a user data portion of a data storage device, and storing the authentication data in a meta data portion of the data storage device.

Abstract: A method and apparatus that allows a snoop phase of a memory transaction to be shortened or skipped is described. During processing of a present memory transaction, the ownership of a system bus during previous memory transactions, as well as the data addresses requested for those transactions, are tracked. If the ownership and requested address of the present transaction match those from the previous transaction, a Next Address signal is provided that allows another transaction to proceed before the snoop phase of the present transaction is completed. In alternate embodiments, the ownership and addresses for multiple transactions are tracked and compared with the ownership and addresses of the present transaction. If a match occurs, the Next Address signal is asserted.

Abstract: Components of a computer system are coupled using a data path application specific integrated circuit (ASIC) crossbar switch. A plurality of multi-bit bi-directional register ports are intercoupled using multi-bit multiplexer circuitry. Port selection control signals provided to the multiplexer direct the flow of data through the data path ASIC. The data path ASIC electrically isolates the components of the computer system, thereby minimizing the capacitive load on signal lines and permitting signals to transfer at high rates of speed. Control of the data path ASIC is provided by external circuitry to increase the flexibility of the crossbar switch by removing dependency on any particular communications protocol. Multiple data path ASICs may be combined in parallel to increase bandwidth of data flow by using a bit slice scheme.

Abstract: Components of a computer system are coupled using a data path application specific integrated circuit (ASIC) crossbar switch. A plurality of multi-bit bi-directional register ports are intercoupled using multi-bit multiplexer circuitry. Port selection control signals provided to the multiplexer direct the flow of data through the data path ASIC. The data path ASIC electrically isolates the components of the computer system, thereby minimizing the capacitive load on signal lines and permitting signals to transfer at high rates of speed. Control of the data path ASIC is provided by external circuitry to increase the flexibility of the crossbar switch by removing dependency on any particular communications protocol. Multiple data path ASICs may be combined in parallel to increase bandwidth of data flow by using a bit slice scheme.