Patents by Inventor Paul E. Riley

Paul E. Riley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4839311
    Abstract: An improved method for the etch-back planarization of interlevel dielectric layers provides for cessation of the etch-back upon exposure of an indicator layer. the indicator layer, usually a metal, metal nitride, or silicon nitride is formed either within the dielectric or over an underlying metallization layer prior to patterning by conventional photolithographic techniques. A sacrificial layer, typically an organic photoresist, is then formed over the dielectric layer. Because of the presence of both relatively narrow and relatively broad features in the metallization, the thickness of the sacrificial layer will vary over features having different widths. As etch back planarization proceeds, the indicator layer which is first encountered releases detectable species into the planarization reactor. Detection of these species indicates that removal of the overlying dielectric layers to a predetermined depth is achieved.
    Type: Grant
    Filed: November 21, 1988
    Date of Patent: June 13, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Paul E. Riley, Vivek D. Kulkarni, Egil D. Castel
  • Patent number: 4676868
    Abstract: A method for planarizing an insulating layer overlying an irregular topographic substrate, e.g., a conductive layer, is planarized by use of a sacrificial planarization layer. The planarization layer is removed using an oxygen-containing plasma generated in a parallel electrode reactor operating at a low excitation frequency and high pressure. Once the interface between the planarization layer and the conductive layer is reached, a second plasma with a reduced oxygen content is employed to avoid overetching the planarization layer. It has been observed that oxidizing species liberated during the etching of the insulating layer, typically silicon dioxide, contribute to the oxidation and hence removal of the planarization layer.
    Type: Grant
    Filed: April 23, 1986
    Date of Patent: June 30, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Paul E. Riley, Alan B. Ray, Paul Bayer