Abstract: Determining a signal emitter location involves receiving a signal of interest (SOI) at detection devices, generating a time stamp corresponding to the arrival of the SOI at each detection device, and communicating digital data samples and the time stamp to a time-difference of arrival (TDOA) computer system. The TDOA computer system determines a TDOA of the SOI at the detection devices relative to an arrival time at a first one of the detection devices having an earliest time stamp. It determines a first solution to identify the emitter location in accordance with a first TDOA solution method. It evaluates the reliability of the first solution and selectively uses a second solution if the first solution is insufficiently reliable.

Abstract: Determining a signal emitter location involves receiving a signal of interest (SOI) at detection devices, generating a time stamp corresponding to the arrival of the SOI at each detection device, and communicating digital data samples and the time stamp to a time-difference of arrival (TDOA) computer system. The TDOA computer system determines a TDOA of the SOI at the detection devices relative to an arrival time at a first one of the detection devices having an earliest time stamp. It determines a first solution to identify the emitter location in accordance with a first TDOA solution method. It evaluates the reliability of the first solution and selectively uses a second solution if the first solution is insufficiently reliable.

Abstract: A communication network may be uncooperative with an uncooperative communications device. The communication network includes mobile wireless communications devices including a collection device and forward devices. Each forward device is configured to detect a received signal characteristic associated with the uncooperative communications device, and transmit the received signal characteristic to the collection device. The collection device is configured to selectively schedule reception of the received signal characteristic based upon a timing of communications among the forward devices, and determine a parameter associated with the uncooperative communications device based upon the received signal characteristic.

Abstract: A communication network may be uncooperative with an uncooperative communications device. The communication network includes mobile wireless communications devices including a collection device and forward devices. Each forward device is configured to detect a received signal characteristic associated with the uncooperative communications device, and transmit the received signal characteristic to the collection device. The collection device is configured to selectively schedule reception of the received signal characteristic based upon a timing of communications among the forward devices, and determine a parameter associated with the uncooperative communications device based upon the received signal characteristic.

Abstract: A system and method is disclosed for maintaining synchronization in a communication system in which a signal is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. If the difference in the output signals of the Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter. A synchronization loss detector may also be used to prevent the phase error signal from updating the phase lock loop filter if synchronization loss is detected.

Abstract: A communication system from maintaining synchronization includes a communication signal comprising a carrier and a data signal that is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. A delay circuit is placed in series with the quick decision circuit to compensate for the traceback delay in the Viterbi decoder. If the difference in the output signals of Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter.

Abstract: A system and method for demodulating a data packet in an automatic repeat request communication system is disclosed. Specifically, in a communication system that combines the energy of an initially transmitted data packet with the energy of a retransmitted version of the data packet, the inventive system and method measures the “usability” of the initially transmitted data packet that fails an error-checking procedure and the “usability” of a retransmitted version of the data packet. If the initially transmitted version and the retransmitted version of the data packet are both “usable”, the energies of the data packets are combined. The combined data packet is then subjected to the error-checking procedure. If the combined data packet fails the error-checking procedure, the energy of either the combined packet or the retransmitted packet is stored for later combination with a subsequently-retransmitted version of the data packet.

Abstract: A novel system and method is disclosed for maintaining synchronization in a communication system in which a communication signal comprising a carrier and a data signal is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. A delay circuit is placed in series with the quick decision circuit to compensate for the traceback delay in the Viterbi decoder. If the difference in the output signals of the Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter.

Abstract: A system and method for demodulating a data packet in an automatic repeat request communication system is disclosed. Specifically, in a communication system that combines the energy of an initially transmitted data packet with the energy of a retransmitted version of the data packet, the inventive system and method measures the “usability” of the initially transmitted data packet that fails an error-checking procedure and the “usability” of a retransmitted version of the data packet. If the initially transmitted version and the retransmitted version of the data packet are both “usable”, the energies of the data packets are combined. The combined data packet is then subjected to the error-checking procedure. If the combined data packet fails the error-checking procedure, the energy of either the combined packet or the retransmitted packet is stored for later combination with a subsequently-retransmitted version of the data packet.

Abstract: A method and apparatus for estimating the frequency of a carrier signal associated with a modulated signal carrying digital data in which the signal is demodulated by a demodulator that includes a numerical controlled oscillator and a least squares fit regression analysis is performed on phase samples of the digital output of the demodulator to provide the slope of the phase, i.e. the frequency offset from the carrier signal. The frequency offset information may be used to adjust the numerical controlled oscillator.

Abstract: A reconfigurable radio frequency communication system. The system includes a receiver subsystem and a signal processing system. The receiver subsystem may be configured to operate in the receiver or transmitter mode of operation. The receiver subsystem may also be configured to handle a plurality of signaling schemes and waveforms. The signal processing system may be tailored with corresponding parameters for performing polar conversion, trellis modulation decoding, and frequency estimation and control.

Abstract: A system and method for providing a field configurable radio frequency communication system including an intermediate frequency digital signal processing circuit therefor. The intermediate frequency digital signal processing circuits includes digital transmitter and receiver circuit paths, a digital baseband circuit, control registers and an interface circuit. The transmitter and receiver circuit paths and the baseband circuits include digital processing circuits that are configurable by commands provided to the control register via the interface circuit to select the transmitter or receiver mode of operation, to select the signaling scheme of waveform employed, to configure the signal processing functions of the transmitter or receiver circuit paths, and to select the use of any of a plurality a baseband signal processing functions.