Patents by Inventor Paul Eric Dahlen
Paul Eric Dahlen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8174103Abstract: A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip.Type: GrantFiled: May 1, 2008Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 8079134Abstract: A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.Type: GrantFiled: August 1, 2008Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Andrew Benson Maki, Gerald Keith Bartley, Philip Raymond Germann, Mark Owen Maxson, Darryl John Becker, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7989918Abstract: A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.Type: GrantFiled: January 26, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7954081Abstract: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.Type: GrantFiled: November 21, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Trevor Joseph Timpane
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Patent number: 7945883Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.Type: GrantFiled: July 14, 2008Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7882479Abstract: A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.Type: GrantFiled: October 15, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis
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Patent number: 7852103Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.Type: GrantFiled: April 24, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Dennis Martin Rickert
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Patent number: 7844769Abstract: A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.Type: GrantFiled: July 26, 2006Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20100271046Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Dennis Martin Rickert
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Publication number: 20100187525Abstract: A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7725762Abstract: A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.Type: GrantFiled: June 6, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis
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Patent number: 7723816Abstract: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.Type: GrantFiled: August 6, 2008Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7675164Abstract: A heat sink apparatus having a plurality of chips attached to a first surface of a flexible carrier and a plurality of heat sink fins. One or more additional chips may be attached to a second surface of the flexible carrier. The flexible carrier has at least one complementary fold, the complementary fold having a counterclockwise fold and a clockwise fold as seen from the side. A first chip back surface of a first chip and a second chip back surface of a second chip are in thermal contact with a particular heat sink fin, that is, sharing the same heat sink fin. Thermal contact between the chips and heat sink fins is effected by force, by thermally conducting adhesive, by thermal grease, or by a combination of force and/or thermally conducting adhesive and/or thermal grease.Type: GrantFiled: March 6, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7673093Abstract: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.Type: GrantFiled: July 26, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20100032799Abstract: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7660942Abstract: A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the address/command word is directed to the memory chip. If so, the array on the memory chip is accessed according to the address command word. If the address/command word is not directed to the memory chip, the memory chip re-drives the address/command word from an output of the memory chip.Type: GrantFiled: July 26, 2006Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7660940Abstract: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.Type: GrantFiled: July 26, 2006Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20100024202Abstract: This invention utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.Type: ApplicationFiled: August 1, 2008Publication date: February 4, 2010Inventors: Andrew Benson Maki, Gerald Keith Bartley, Philip Raymond Germann, Mark Owen Maxson, Darryl John Becker, Paul Eric Dahlen, John Edward Sheets, II
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Publication number: 20100019385Abstract: Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material.Type: ApplicationFiled: July 23, 2008Publication date: January 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Publication number: 20090300411Abstract: A method and apparatus implement redundant memory access using multiple controllers for a memory system, and a design structure on which the subject circuit resides are provided. A first memory controller uses a first memory and a second memory controller uses the second memory as its respective primary address space, for storage and fetches. The second memory controller is also connected to the first memory. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. When one of the first memory controller or the second memory controller fails, then the other memory controller is notified. The other memory controller takes control of the memory for the failed controller, using the direct connection to that memory, and maintains coherence of both the first memory and second memory.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson