Patents by Inventor Paul-Etienne Joseph VIDAL

Paul-Etienne Joseph VIDAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847494
    Abstract: Some embodiments are directed to a method of determining a sintering thermal impedance of a sintering layer by: providing a substrate having a predetermined substrate thermal impedance and disposing the sintering layer on the substrate forming with the sintering layer a stack. Placing at least one semiconductor die, that includes a semiconductor element with at least two element electrodes on the sintering layer. Injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element. Heating the stack with a predetermined heat power and determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 24, 2020
    Assignees: AGILE POWER SWITCH 3D-INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE), ECOLE NATIONALE D'INGENIEURS DE TARBES
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaël Riva, Paul-Etienne Joseph Vidal, Baptiste Louis Jean Trajin
  • Publication number: 20200043885
    Abstract: A method of determining a sintering thermal impedance of a sintering layer (25) comprising: providing a substrate (20) having a predetermined substrate thermal impedance, disposing the sintering layer (25) on the substrate (20) forming with the sintering layer (25) a stack, placing at least one semiconductor die (30) comprising a semiconductor element (40) with at least two element electrodes (45; 47) on the sintering layer (25), injecting an electrical current through the at least two element electrodes (45; 47) for measuring a temperature sensitive parameter of the semiconductor element (40), heating the stack with a predetermined heat power, determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter, measuring a stack temperature, determining a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature and dividing by the predetermined heat power, and subtracting the predetermined substrate thermal impedan
    Type: Application
    Filed: October 2, 2017
    Publication date: February 6, 2020
    Inventors: Jacques Pierre Henri FAVRE, Jean-Michel Francis REYNES, Raphaël RIVA, Paul-Etienne Joseph VIDAL, Baptiste Louis Jean TRAJIN