Abstract: In a data processing system having a plurality of channels that are organized for separately processing the operations of specific I/O devices and the operations that are background to these specific operations, apparatus for transferring the background processing from one channel to another channel to distribute the background processing load. A system of registers and lines connect these registers to the channels for controlling these operations. Each channel processor has a request register for use in designating that background processing has been completed and that processing of a device oriented portion of a channel program is to begin, and a completion register set by an associated I/O processor for use in signifying that processing of a device oriented portion of a channel program has been completed and that background processing is to begin.

Abstract: Apparatus for signalling the occurrence of a match between an address that is supplied to a control store and an address that is to be watched for in a data processing system that executes several instruction streams concurrently. The apparatus signals the occurrence of a storage accessing operation at a location that is uniquely identified only by a virtual address that is longer than the actual address used in accessing the store. Means is provided for comparing the actual address used in accessing the store with the corresponding portion of the complete address, and means is provided for recording the location of an address to be watched for in a particular frame of the store and for signalling a match that occurs in such a frame. The apparatus is useful for testing the operation of the data processing system by relating a recurring malfunction of the system to the execution of an instruction at the address that is watched for.