Abstract: Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Abstract: Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Abstract: A data processing device is described which at least comprises a master controller (1), a first functional unit (2) which includes a slave controller (20), a second functional unit (3). The functional units (2,3) share common memory means (11). The device is programmed for executing an instruction by the first functional unit (2), the execution of said instruction involving input/output operations by the first functional unit (3), wherein output data of the first functional unit (2) is processed by the second functional unit (3) during said execution and/or the input data is generated by the second functional (3) unit during said execution.