Abstract: Methods and apparatuses for clock signal phase measurement and control are described. In one example, a clock signal phase measurement system includes a reference clock signal line to provide a reference clock signal, a delay line to provide an output clock signal, and a wild clock. The clock signal phase measurement system includes a phase sensor configured to randomly and simultaneously sample the reference clock signal and the output clock signal utilizing the wild clock to obtain a phase data. The phase sensor is further configured to measure from the phase data a phase difference between the reference clock signal and the output clock signal.

Abstract: A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal.

Abstract: The present invention comprises a dynamic skew compensation circuit. The present invention includes a receiver, a plurality of channel inputs built into the receiver, and a delay stack structure coupled to the plurality of channel inputs. The receiver is adapted to accept data from a parallel data transfer cable. The channel inputs couple to each of the individual communications channels which comprise the parallel data transfer cable. The delay stack structure includes a plurality of delay stacks, each coupled to a respective channel input. Each delay stack dynamically selects an additional delay amount for its respective communications channel such that each communications channel of the parallel data transfer cable is deskewed with respect to the others. In so doing, the distances across which data can be received and the speeds at which data is transferred via the parallel data transfer cable is increased.