Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.

Abstract: A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.

Abstract: A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.

Abstract: A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.

Abstract: A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.

Abstract: A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.