Abstract: A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.

Abstract: A computer-implemented method is disclosed for recognizing edges in a digital image having a plurality of pixels with gray-scale values defining features. The method includes recognizing edges of the features by cearting a new image in which pixels in the new image corresponding to pixels in the gray-scale image that have a brightness value meeting a predetermined threshold are assigned a first binary value to represent edge regions, while remaining pixels in the new image are assigned a second value to represent both background and internal areas of the features. Area recognition is then performed to distinguish internal feature areas from background areas. The method further includes detecting edge lines from the edge regions that separate features from background and internal feature areas.

Abstract: A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.

Abstract: A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and at least one of the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Abstract: A method and system for automatically calibrating a masking process simulator are disclosed. The method and system include performing a masking process using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected from the digital image using pattern recognition. Data defining the calibration mask and the process parameters are then input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The method and system further include overlaying the alim image and the detected edges of the digital image, and measuring a distance between contours of the pattern in the alim image and the detected edges.

Abstract: An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Abstract: A method and system for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Abstract: A computer-implemented method is disclosed for recognizing edges in a digital image having a plurality of pixels with gray-scale values defining features. The method includes recognizing edges of the features by cearting a new image in which pixels in the new image corresponding to pixels in the gray-scale image that have a brightness value meeting a predetermined threshold are assigned a first binary value to represent edge regions, while remaining pixels in the new image are assigned a second value to represent both background and internal areas of the features. Area recognition is then performed to distinguish internal feature areas from background areas. The method further includes detecting edge lines from the edge regions that separate features from background and internal feature areas.

Abstract: A method and system for automatically calibrating a masking process simulator are disclosed. The method and system include performing a masking process using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected from the digital image using pattern recognition. Data defining the calibration mask and the process parameters are then input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The method and system further include overlaying the alim image and the detected edges of the digital image, and measuring a distance between contours of the pattern in the alim image and the detected edges.

Abstract: A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

Abstract: An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Abstract: The invention describes a method for expanding (flattening) hierarchical descriptions of electronic circuits into flat descriptions. The method is characterized by two processes: one which eliminates feed-through and implicit signals, and another which pre-plans the layout of the flattened data structure before flattening. The flattening process may then take advantage of a number of resulting efficiencies to operate more quickly than present flatteners.